1*4882a593Smuzhiyun# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2*4882a593Smuzhiyun%YAML 1.2
3*4882a593Smuzhiyun---
4*4882a593Smuzhiyun$id: http://devicetree.org/schemas/memory-controllers/calxeda-ddr-ctrlr.yaml#
5*4882a593Smuzhiyun$schema: http://devicetree.org/meta-schemas/core.yaml#
6*4882a593Smuzhiyun
7*4882a593Smuzhiyuntitle: Calxeda DDR memory controller binding
8*4882a593Smuzhiyun
9*4882a593Smuzhiyundescription: |
10*4882a593Smuzhiyun  The Calxeda DDR memory controller is initialised and programmed by the
11*4882a593Smuzhiyun  firmware, but an OS might want to read its registers for error reporting
12*4882a593Smuzhiyun  purposes and to learn about the DRAM topology.
13*4882a593Smuzhiyun
14*4882a593Smuzhiyunmaintainers:
15*4882a593Smuzhiyun  - Andre Przywara <andre.przywara@arm.com>
16*4882a593Smuzhiyun
17*4882a593Smuzhiyunproperties:
18*4882a593Smuzhiyun  compatible:
19*4882a593Smuzhiyun    enum:
20*4882a593Smuzhiyun      - calxeda,hb-ddr-ctrl
21*4882a593Smuzhiyun      - calxeda,ecx-2000-ddr-ctrl
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun  reg:
24*4882a593Smuzhiyun    maxItems: 1
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun  interrupts:
27*4882a593Smuzhiyun    maxItems: 1
28*4882a593Smuzhiyun
29*4882a593Smuzhiyunrequired:
30*4882a593Smuzhiyun  - compatible
31*4882a593Smuzhiyun  - reg
32*4882a593Smuzhiyun  - interrupts
33*4882a593Smuzhiyun
34*4882a593SmuzhiyunadditionalProperties: false
35*4882a593Smuzhiyun
36*4882a593Smuzhiyunexamples:
37*4882a593Smuzhiyun  - |
38*4882a593Smuzhiyun    memory-controller@fff00000 {
39*4882a593Smuzhiyun        compatible = "calxeda,hb-ddr-ctrl";
40*4882a593Smuzhiyun        reg = <0xfff00000 0x1000>;
41*4882a593Smuzhiyun        interrupts = <0 91 4>;
42*4882a593Smuzhiyun    };
43