1*4882a593SmuzhiyunDDR PHY Front End (DPFE) for Broadcom STB 2*4882a593Smuzhiyun========================================= 3*4882a593Smuzhiyun 4*4882a593SmuzhiyunDPFE and the DPFE firmware provide an interface for the host CPU to 5*4882a593Smuzhiyuncommunicate with the DCPU, which resides inside the DDR PHY. 6*4882a593Smuzhiyun 7*4882a593SmuzhiyunThere are three memory regions for interacting with the DCPU. These are 8*4882a593Smuzhiyunspecified in a single reg property. 9*4882a593Smuzhiyun 10*4882a593SmuzhiyunRequired properties: 11*4882a593Smuzhiyun - compatible: must be "brcm,bcm7271-dpfe-cpu", "brcm,bcm7268-dpfe-cpu" 12*4882a593Smuzhiyun or "brcm,dpfe-cpu" 13*4882a593Smuzhiyun - reg: must reference three register ranges 14*4882a593Smuzhiyun - start address and length of the DCPU register space 15*4882a593Smuzhiyun - start address and length of the DCPU data memory space 16*4882a593Smuzhiyun - start address and length of the DCPU instruction memory space 17*4882a593Smuzhiyun - reg-names: must contain "dpfe-cpu", "dpfe-dmem", and "dpfe-imem"; 18*4882a593Smuzhiyun they must be in the same order as the register declarations 19*4882a593Smuzhiyun 20*4882a593SmuzhiyunExample: 21*4882a593Smuzhiyun dpfe_cpu0: dpfe-cpu@f1132000 { 22*4882a593Smuzhiyun compatible = "brcm,bcm7271-dpfe-cpu", "brcm,dpfe-cpu"; 23*4882a593Smuzhiyun reg = <0xf1132000 0x180 24*4882a593Smuzhiyun 0xf1134000 0x1000 25*4882a593Smuzhiyun 0xf1138000 0x4000>; 26*4882a593Smuzhiyun reg-names = "dpfe-cpu", "dpfe-dmem", "dpfe-imem"; 27*4882a593Smuzhiyun }; 28