1*4882a593Smuzhiyun# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*4882a593Smuzhiyun# Copyright (C) 2020 BAIKAL ELECTRONICS, JSC 3*4882a593Smuzhiyun%YAML 1.2 4*4882a593Smuzhiyun--- 5*4882a593Smuzhiyun$id: http://devicetree.org/schemas/memory-controllers/baikal,bt1-l2-ctl.yaml# 6*4882a593Smuzhiyun$schema: http://devicetree.org/meta-schemas/core.yaml# 7*4882a593Smuzhiyun 8*4882a593Smuzhiyuntitle: Baikal-T1 L2-cache Control Block 9*4882a593Smuzhiyun 10*4882a593Smuzhiyunmaintainers: 11*4882a593Smuzhiyun - Serge Semin <fancer.lancer@gmail.com> 12*4882a593Smuzhiyun 13*4882a593Smuzhiyundescription: | 14*4882a593Smuzhiyun By means of the System Controller Baikal-T1 SoC exposes a few settings to 15*4882a593Smuzhiyun tune the MIPS P5600 CM2 L2 cache performance up. In particular it's possible 16*4882a593Smuzhiyun to change the Tag, Data and Way-select RAM access latencies. Baikal-T1 17*4882a593Smuzhiyun L2-cache controller block is responsible for the tuning. Its DT node is 18*4882a593Smuzhiyun supposed to be a child of the system controller. 19*4882a593Smuzhiyun 20*4882a593Smuzhiyunproperties: 21*4882a593Smuzhiyun compatible: 22*4882a593Smuzhiyun const: baikal,bt1-l2-ctl 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun reg: 25*4882a593Smuzhiyun maxItems: 1 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun baikal,l2-ws-latency: 28*4882a593Smuzhiyun $ref: /schemas/types.yaml#/definitions/uint32 29*4882a593Smuzhiyun description: Cycles of latency for Way-select RAM accesses 30*4882a593Smuzhiyun default: 0 31*4882a593Smuzhiyun minimum: 0 32*4882a593Smuzhiyun maximum: 3 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun baikal,l2-tag-latency: 35*4882a593Smuzhiyun $ref: /schemas/types.yaml#/definitions/uint32 36*4882a593Smuzhiyun description: Cycles of latency for Tag RAM accesses 37*4882a593Smuzhiyun default: 0 38*4882a593Smuzhiyun minimum: 0 39*4882a593Smuzhiyun maximum: 3 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun baikal,l2-data-latency: 42*4882a593Smuzhiyun $ref: /schemas/types.yaml#/definitions/uint32 43*4882a593Smuzhiyun description: Cycles of latency for Data RAM accesses 44*4882a593Smuzhiyun default: 1 45*4882a593Smuzhiyun minimum: 0 46*4882a593Smuzhiyun maximum: 3 47*4882a593Smuzhiyun 48*4882a593SmuzhiyunadditionalProperties: false 49*4882a593Smuzhiyun 50*4882a593Smuzhiyunrequired: 51*4882a593Smuzhiyun - compatible 52*4882a593Smuzhiyun 53*4882a593Smuzhiyunexamples: 54*4882a593Smuzhiyun - | 55*4882a593Smuzhiyun l2@1f04d028 { 56*4882a593Smuzhiyun compatible = "baikal,bt1-l2-ctl"; 57*4882a593Smuzhiyun reg = <0x1f04d028 0x004>; 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun baikal,l2-ws-latency = <1>; 60*4882a593Smuzhiyun baikal,l2-tag-latency = <1>; 61*4882a593Smuzhiyun baikal,l2-data-latency = <2>; 62*4882a593Smuzhiyun }; 63*4882a593Smuzhiyun... 64