1*4882a593Smuzhiyun* Device tree bindings for ARM PL172/PL175/PL176 MultiPort Memory Controller 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunRequired properties: 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun- compatible: Must be "arm,primecell" and exactly one from 6*4882a593Smuzhiyun "arm,pl172", "arm,pl175" or "arm,pl176". 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun- reg: Must contains offset/length value for controller. 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun- #address-cells: Must be 2. The partition number has to be encoded in the 11*4882a593Smuzhiyun first address cell and it may accept values 0..N-1 12*4882a593Smuzhiyun (N - total number of partitions). The second cell is the 13*4882a593Smuzhiyun offset into the partition. 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun- #size-cells: Must be set to 1. 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun- ranges: Must contain one or more chip select memory regions. 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun- clocks: Must contain references to controller clocks. 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun- clock-names: Must contain "mpmcclk" and "apb_pclk". 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun- clock-ranges: Empty property indicating that child nodes can inherit 24*4882a593Smuzhiyun named clocks. Required only if clock tree data present 25*4882a593Smuzhiyun in device tree. 26*4882a593Smuzhiyun See clock-bindings.txt 27*4882a593Smuzhiyun 28*4882a593SmuzhiyunChild chip-select (cs) nodes contain the memory devices nodes connected to 29*4882a593Smuzhiyunsuch as NOR (e.g. cfi-flash) and NAND. 30*4882a593Smuzhiyun 31*4882a593SmuzhiyunRequired child cs node properties: 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun- #address-cells: Must be 2. 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun- #size-cells: Must be 1. 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun- ranges: Empty property indicating that child nodes can inherit 38*4882a593Smuzhiyun memory layout. 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun- clock-ranges: Empty property indicating that child nodes can inherit 41*4882a593Smuzhiyun named clocks. Required only if clock tree data present 42*4882a593Smuzhiyun in device tree. 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun- mpmc,cs: Chip select number. Indicates to the pl0172 driver 45*4882a593Smuzhiyun which chipselect is used for accessing the memory. 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun- mpmc,memory-width: Width of the chip select memory. Must be equal to 48*4882a593Smuzhiyun either 8, 16 or 32. 49*4882a593Smuzhiyun 50*4882a593SmuzhiyunOptional child cs node config properties: 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun- mpmc,async-page-mode: Enable asynchronous page mode. 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun- mpmc,cs-active-high: Set chip select polarity to active high. 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun- mpmc,byte-lane-low: Set byte lane state to low. 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun- mpmc,extended-wait: Enable extended wait. 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun- mpmc,buffer-enable: Enable write buffer, option is not supported by 61*4882a593Smuzhiyun PL175 and PL176 controllers. 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun- mpmc,write-protect: Enable write protect. 64*4882a593Smuzhiyun 65*4882a593SmuzhiyunOptional child cs node timing properties: 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun- mpmc,write-enable-delay: Delay from chip select assertion to write 68*4882a593Smuzhiyun enable (WE signal) in nano seconds. 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun- mpmc,output-enable-delay: Delay from chip select assertion to output 71*4882a593Smuzhiyun enable (OE signal) in nano seconds. 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun- mpmc,write-access-delay: Delay from chip select assertion to write 74*4882a593Smuzhiyun access in nano seconds. 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun- mpmc,read-access-delay: Delay from chip select assertion to read 77*4882a593Smuzhiyun access in nano seconds. 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun- mpmc,page-mode-read-delay: Delay for asynchronous page mode sequential 80*4882a593Smuzhiyun accesses in nano seconds. 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun- mpmc,turn-round-delay: Delay between access to memory banks in nano 83*4882a593Smuzhiyun seconds. 84*4882a593Smuzhiyun 85*4882a593SmuzhiyunIf any of the above timing parameters are absent, current parameter value will 86*4882a593Smuzhiyunbe taken from the corresponding HW reg. 87*4882a593Smuzhiyun 88*4882a593SmuzhiyunExample for pl172 with nor flash on chip select 0 shown below. 89*4882a593Smuzhiyun 90*4882a593Smuzhiyunemc: memory-controller@40005000 { 91*4882a593Smuzhiyun compatible = "arm,pl172", "arm,primecell"; 92*4882a593Smuzhiyun reg = <0x40005000 0x1000>; 93*4882a593Smuzhiyun clocks = <&ccu1 CLK_CPU_EMCDIV>, <&ccu1 CLK_CPU_EMC>; 94*4882a593Smuzhiyun clock-names = "mpmcclk", "apb_pclk"; 95*4882a593Smuzhiyun #address-cells = <2>; 96*4882a593Smuzhiyun #size-cells = <1>; 97*4882a593Smuzhiyun ranges = <0 0 0x1c000000 0x1000000 98*4882a593Smuzhiyun 1 0 0x1d000000 0x1000000 99*4882a593Smuzhiyun 2 0 0x1e000000 0x1000000 100*4882a593Smuzhiyun 3 0 0x1f000000 0x1000000>; 101*4882a593Smuzhiyun 102*4882a593Smuzhiyun cs0 { 103*4882a593Smuzhiyun #address-cells = <2>; 104*4882a593Smuzhiyun #size-cells = <1>; 105*4882a593Smuzhiyun ranges; 106*4882a593Smuzhiyun 107*4882a593Smuzhiyun mpmc,cs = <0>; 108*4882a593Smuzhiyun mpmc,memory-width = <16>; 109*4882a593Smuzhiyun mpmc,byte-lane-low; 110*4882a593Smuzhiyun mpmc,write-enable-delay = <0>; 111*4882a593Smuzhiyun mpmc,output-enable-delay = <0>; 112*4882a593Smuzhiyun mpmc,read-enable-delay = <70>; 113*4882a593Smuzhiyun mpmc,page-mode-read-delay = <70>; 114*4882a593Smuzhiyun 115*4882a593Smuzhiyun flash@0,0 { 116*4882a593Smuzhiyun compatible = "sst,sst39vf320", "cfi-flash"; 117*4882a593Smuzhiyun reg = <0 0 0x400000>; 118*4882a593Smuzhiyun bank-width = <2>; 119*4882a593Smuzhiyun #address-cells = <1>; 120*4882a593Smuzhiyun #size-cells = <1>; 121*4882a593Smuzhiyun partition@0 { 122*4882a593Smuzhiyun label = "data"; 123*4882a593Smuzhiyun reg = <0 0x400000>; 124*4882a593Smuzhiyun }; 125*4882a593Smuzhiyun }; 126*4882a593Smuzhiyun }; 127*4882a593Smuzhiyun}; 128