1*4882a593SmuzhiyunXilinx Video Test Pattern Generator (TPG) 2*4882a593Smuzhiyun----------------------------------------- 3*4882a593Smuzhiyun 4*4882a593SmuzhiyunRequired properties: 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun- compatible: Must contain at least one of 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun "xlnx,v-tpg-5.0" (TPG version 5.0) 9*4882a593Smuzhiyun "xlnx,v-tpg-6.0" (TPG version 6.0) 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun TPG versions backward-compatible with previous versions should list all 12*4882a593Smuzhiyun compatible versions in the newer to older order. 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun- reg: Physical base address and length of the registers set for the device. 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun- clocks: Reference to the video core clock. 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun- xlnx,video-format, xlnx,video-width: Video format and width, as defined in 19*4882a593Smuzhiyun video.txt. 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun- port: Video port, using the DT bindings defined in ../video-interfaces.txt. 22*4882a593Smuzhiyun The TPG has a single output port numbered 0. 23*4882a593Smuzhiyun 24*4882a593SmuzhiyunOptional properties: 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun- xlnx,vtc: A phandle referencing the Video Timing Controller that generates 27*4882a593Smuzhiyun video timings for the TPG test patterns. 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun- timing-gpios: Specifier for a GPIO that controls the timing mux at the TPG 30*4882a593Smuzhiyun input. The GPIO active level corresponds to the selection of VTC-generated 31*4882a593Smuzhiyun video timings. 32*4882a593Smuzhiyun 33*4882a593SmuzhiyunThe xlnx,vtc and timing-gpios properties are mandatory when the TPG is 34*4882a593Smuzhiyunsynthesized with two ports and forbidden when synthesized with one port. 35*4882a593Smuzhiyun 36*4882a593SmuzhiyunExample: 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun tpg_0: tpg@40050000 { 39*4882a593Smuzhiyun compatible = "xlnx,v-tpg-6.0", "xlnx,v-tpg-5.0"; 40*4882a593Smuzhiyun reg = <0x40050000 0x10000>; 41*4882a593Smuzhiyun clocks = <&clkc 15>; 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun xlnx,vtc = <&vtc_3>; 44*4882a593Smuzhiyun timing-gpios = <&ps7_gpio_0 55 GPIO_ACTIVE_LOW>; 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun ports { 47*4882a593Smuzhiyun #address-cells = <1>; 48*4882a593Smuzhiyun #size-cells = <0>; 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun port@0 { 51*4882a593Smuzhiyun reg = <0>; 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun xlnx,video-format = <XVIP_VF_YUV_422>; 54*4882a593Smuzhiyun xlnx,video-width = <8>; 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun tpg_in: endpoint { 57*4882a593Smuzhiyun remote-endpoint = <&adv7611_out>; 58*4882a593Smuzhiyun }; 59*4882a593Smuzhiyun }; 60*4882a593Smuzhiyun port@1 { 61*4882a593Smuzhiyun reg = <1>; 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun xlnx,video-format = <XVIP_VF_YUV_422>; 64*4882a593Smuzhiyun xlnx,video-width = <8>; 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun tpg1_out: endpoint { 67*4882a593Smuzhiyun remote-endpoint = <&switch_in0>; 68*4882a593Smuzhiyun }; 69*4882a593Smuzhiyun }; 70*4882a593Smuzhiyun }; 71*4882a593Smuzhiyun }; 72