1*4882a593Smuzhiyun# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*4882a593Smuzhiyun%YAML 1.2 3*4882a593Smuzhiyun--- 4*4882a593Smuzhiyun$id: http://devicetree.org/schemas/media/xilinx/xlnx,csi2rxss.yaml# 5*4882a593Smuzhiyun$schema: http://devicetree.org/meta-schemas/core.yaml# 6*4882a593Smuzhiyun 7*4882a593Smuzhiyuntitle: Xilinx MIPI CSI-2 Receiver Subsystem 8*4882a593Smuzhiyun 9*4882a593Smuzhiyunmaintainers: 10*4882a593Smuzhiyun - Vishal Sagar <vishal.sagar@xilinx.com> 11*4882a593Smuzhiyun 12*4882a593Smuzhiyundescription: | 13*4882a593Smuzhiyun The Xilinx MIPI CSI-2 Receiver Subsystem is used to capture MIPI CSI-2 14*4882a593Smuzhiyun traffic from compliant camera sensors and send the output as AXI4 Stream 15*4882a593Smuzhiyun video data for image processing. 16*4882a593Smuzhiyun The subsystem consists of a MIPI D-PHY in slave mode which captures the 17*4882a593Smuzhiyun data packets. This is passed along the MIPI CSI-2 Rx IP which extracts the 18*4882a593Smuzhiyun packet data. The optional Video Format Bridge (VFB) converts this data to 19*4882a593Smuzhiyun AXI4 Stream video data. 20*4882a593Smuzhiyun For more details, please refer to PG232 Xilinx MIPI CSI-2 Receiver Subsystem. 21*4882a593Smuzhiyun Please note that this bindings includes only the MIPI CSI-2 Rx controller 22*4882a593Smuzhiyun and Video Format Bridge and not D-PHY. 23*4882a593Smuzhiyun 24*4882a593Smuzhiyunproperties: 25*4882a593Smuzhiyun compatible: 26*4882a593Smuzhiyun items: 27*4882a593Smuzhiyun - enum: 28*4882a593Smuzhiyun - xlnx,mipi-csi2-rx-subsystem-5.0 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun reg: 31*4882a593Smuzhiyun maxItems: 1 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun interrupts: 34*4882a593Smuzhiyun maxItems: 1 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun clocks: 37*4882a593Smuzhiyun description: List of clock specifiers 38*4882a593Smuzhiyun items: 39*4882a593Smuzhiyun - description: AXI Lite clock 40*4882a593Smuzhiyun - description: Video clock 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun clock-names: 43*4882a593Smuzhiyun items: 44*4882a593Smuzhiyun - const: lite_aclk 45*4882a593Smuzhiyun - const: video_aclk 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun xlnx,csi-pxl-format: 48*4882a593Smuzhiyun description: | 49*4882a593Smuzhiyun This denotes the CSI Data type selected in hw design. 50*4882a593Smuzhiyun Packets other than this data type (except for RAW8 and 51*4882a593Smuzhiyun User defined data types) will be filtered out. 52*4882a593Smuzhiyun Possible values are as below - 53*4882a593Smuzhiyun 0x1e - YUV4228B 54*4882a593Smuzhiyun 0x1f - YUV42210B 55*4882a593Smuzhiyun 0x20 - RGB444 56*4882a593Smuzhiyun 0x21 - RGB555 57*4882a593Smuzhiyun 0x22 - RGB565 58*4882a593Smuzhiyun 0x23 - RGB666 59*4882a593Smuzhiyun 0x24 - RGB888 60*4882a593Smuzhiyun 0x28 - RAW6 61*4882a593Smuzhiyun 0x29 - RAW7 62*4882a593Smuzhiyun 0x2a - RAW8 63*4882a593Smuzhiyun 0x2b - RAW10 64*4882a593Smuzhiyun 0x2c - RAW12 65*4882a593Smuzhiyun 0x2d - RAW14 66*4882a593Smuzhiyun 0x2e - RAW16 67*4882a593Smuzhiyun 0x2f - RAW20 68*4882a593Smuzhiyun $ref: /schemas/types.yaml#/definitions/uint32 69*4882a593Smuzhiyun oneOf: 70*4882a593Smuzhiyun - minimum: 0x1e 71*4882a593Smuzhiyun maximum: 0x24 72*4882a593Smuzhiyun - minimum: 0x28 73*4882a593Smuzhiyun maximum: 0x2f 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun xlnx,vfb: 76*4882a593Smuzhiyun type: boolean 77*4882a593Smuzhiyun description: Present when Video Format Bridge is enabled in IP configuration 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun xlnx,en-csi-v2-0: 80*4882a593Smuzhiyun type: boolean 81*4882a593Smuzhiyun description: Present if CSI v2 is enabled in IP configuration. 82*4882a593Smuzhiyun 83*4882a593Smuzhiyun xlnx,en-vcx: 84*4882a593Smuzhiyun type: boolean 85*4882a593Smuzhiyun description: | 86*4882a593Smuzhiyun When present, there are maximum 16 virtual channels, else only 4. 87*4882a593Smuzhiyun 88*4882a593Smuzhiyun xlnx,en-active-lanes: 89*4882a593Smuzhiyun type: boolean 90*4882a593Smuzhiyun description: | 91*4882a593Smuzhiyun Present if the number of active lanes can be re-configured at 92*4882a593Smuzhiyun runtime in the Protocol Configuration Register. Otherwise all lanes, 93*4882a593Smuzhiyun as set in IP configuration, are always active. 94*4882a593Smuzhiyun 95*4882a593Smuzhiyun video-reset-gpios: 96*4882a593Smuzhiyun description: Optional specifier for a GPIO that asserts video_aresetn. 97*4882a593Smuzhiyun maxItems: 1 98*4882a593Smuzhiyun 99*4882a593Smuzhiyun ports: 100*4882a593Smuzhiyun type: object 101*4882a593Smuzhiyun 102*4882a593Smuzhiyun properties: 103*4882a593Smuzhiyun port@0: 104*4882a593Smuzhiyun type: object 105*4882a593Smuzhiyun description: | 106*4882a593Smuzhiyun Input / sink port node, single endpoint describing the 107*4882a593Smuzhiyun CSI-2 transmitter. 108*4882a593Smuzhiyun 109*4882a593Smuzhiyun properties: 110*4882a593Smuzhiyun reg: 111*4882a593Smuzhiyun const: 0 112*4882a593Smuzhiyun 113*4882a593Smuzhiyun endpoint: 114*4882a593Smuzhiyun type: object 115*4882a593Smuzhiyun 116*4882a593Smuzhiyun properties: 117*4882a593Smuzhiyun 118*4882a593Smuzhiyun data-lanes: 119*4882a593Smuzhiyun description: | 120*4882a593Smuzhiyun This is required only in the sink port 0 endpoint which 121*4882a593Smuzhiyun connects to MIPI CSI-2 source like sensor. 122*4882a593Smuzhiyun The possible values are - 123*4882a593Smuzhiyun 1 - For 1 lane enabled in IP. 124*4882a593Smuzhiyun 1 2 - For 2 lanes enabled in IP. 125*4882a593Smuzhiyun 1 2 3 - For 3 lanes enabled in IP. 126*4882a593Smuzhiyun 1 2 3 4 - For 4 lanes enabled in IP. 127*4882a593Smuzhiyun items: 128*4882a593Smuzhiyun - const: 1 129*4882a593Smuzhiyun - const: 2 130*4882a593Smuzhiyun - const: 3 131*4882a593Smuzhiyun - const: 4 132*4882a593Smuzhiyun 133*4882a593Smuzhiyun remote-endpoint: true 134*4882a593Smuzhiyun 135*4882a593Smuzhiyun required: 136*4882a593Smuzhiyun - data-lanes 137*4882a593Smuzhiyun - remote-endpoint 138*4882a593Smuzhiyun 139*4882a593Smuzhiyun additionalProperties: false 140*4882a593Smuzhiyun 141*4882a593Smuzhiyun additionalProperties: false 142*4882a593Smuzhiyun 143*4882a593Smuzhiyun port@1: 144*4882a593Smuzhiyun type: object 145*4882a593Smuzhiyun description: | 146*4882a593Smuzhiyun Output / source port node, endpoint describing modules 147*4882a593Smuzhiyun connected the CSI-2 receiver. 148*4882a593Smuzhiyun 149*4882a593Smuzhiyun properties: 150*4882a593Smuzhiyun 151*4882a593Smuzhiyun reg: 152*4882a593Smuzhiyun const: 1 153*4882a593Smuzhiyun 154*4882a593Smuzhiyun endpoint: 155*4882a593Smuzhiyun type: object 156*4882a593Smuzhiyun 157*4882a593Smuzhiyun properties: 158*4882a593Smuzhiyun 159*4882a593Smuzhiyun remote-endpoint: true 160*4882a593Smuzhiyun 161*4882a593Smuzhiyun required: 162*4882a593Smuzhiyun - remote-endpoint 163*4882a593Smuzhiyun 164*4882a593Smuzhiyun additionalProperties: false 165*4882a593Smuzhiyun 166*4882a593Smuzhiyun additionalProperties: false 167*4882a593Smuzhiyun 168*4882a593Smuzhiyunrequired: 169*4882a593Smuzhiyun - compatible 170*4882a593Smuzhiyun - reg 171*4882a593Smuzhiyun - interrupts 172*4882a593Smuzhiyun - clocks 173*4882a593Smuzhiyun - clock-names 174*4882a593Smuzhiyun - ports 175*4882a593Smuzhiyun 176*4882a593SmuzhiyunallOf: 177*4882a593Smuzhiyun - if: 178*4882a593Smuzhiyun required: 179*4882a593Smuzhiyun - xlnx,vfb 180*4882a593Smuzhiyun then: 181*4882a593Smuzhiyun required: 182*4882a593Smuzhiyun - xlnx,csi-pxl-format 183*4882a593Smuzhiyun else: 184*4882a593Smuzhiyun properties: 185*4882a593Smuzhiyun xlnx,csi-pxl-format: false 186*4882a593Smuzhiyun 187*4882a593Smuzhiyun - if: 188*4882a593Smuzhiyun not: 189*4882a593Smuzhiyun required: 190*4882a593Smuzhiyun - xlnx,en-csi-v2-0 191*4882a593Smuzhiyun then: 192*4882a593Smuzhiyun properties: 193*4882a593Smuzhiyun xlnx,en-vcx: false 194*4882a593Smuzhiyun 195*4882a593SmuzhiyunadditionalProperties: false 196*4882a593Smuzhiyun 197*4882a593Smuzhiyunexamples: 198*4882a593Smuzhiyun - | 199*4882a593Smuzhiyun #include <dt-bindings/gpio/gpio.h> 200*4882a593Smuzhiyun xcsi2rxss_1: csi2rx@a0020000 { 201*4882a593Smuzhiyun compatible = "xlnx,mipi-csi2-rx-subsystem-5.0"; 202*4882a593Smuzhiyun reg = <0xa0020000 0x10000>; 203*4882a593Smuzhiyun interrupt-parent = <&gic>; 204*4882a593Smuzhiyun interrupts = <0 95 4>; 205*4882a593Smuzhiyun xlnx,csi-pxl-format = <0x2a>; 206*4882a593Smuzhiyun xlnx,vfb; 207*4882a593Smuzhiyun xlnx,en-active-lanes; 208*4882a593Smuzhiyun xlnx,en-csi-v2-0; 209*4882a593Smuzhiyun xlnx,en-vcx; 210*4882a593Smuzhiyun clock-names = "lite_aclk", "video_aclk"; 211*4882a593Smuzhiyun clocks = <&misc_clk_0>, <&misc_clk_1>; 212*4882a593Smuzhiyun video-reset-gpios = <&gpio 86 GPIO_ACTIVE_LOW>; 213*4882a593Smuzhiyun 214*4882a593Smuzhiyun ports { 215*4882a593Smuzhiyun #address-cells = <1>; 216*4882a593Smuzhiyun #size-cells = <0>; 217*4882a593Smuzhiyun 218*4882a593Smuzhiyun port@0 { 219*4882a593Smuzhiyun /* Sink port */ 220*4882a593Smuzhiyun reg = <0>; 221*4882a593Smuzhiyun csiss_in: endpoint { 222*4882a593Smuzhiyun data-lanes = <1 2 3 4>; 223*4882a593Smuzhiyun /* MIPI CSI-2 Camera handle */ 224*4882a593Smuzhiyun remote-endpoint = <&camera_out>; 225*4882a593Smuzhiyun }; 226*4882a593Smuzhiyun }; 227*4882a593Smuzhiyun port@1 { 228*4882a593Smuzhiyun /* Source port */ 229*4882a593Smuzhiyun reg = <1>; 230*4882a593Smuzhiyun csiss_out: endpoint { 231*4882a593Smuzhiyun remote-endpoint = <&vproc_in>; 232*4882a593Smuzhiyun }; 233*4882a593Smuzhiyun }; 234*4882a593Smuzhiyun }; 235*4882a593Smuzhiyun }; 236*4882a593Smuzhiyun... 237