1*4882a593SmuzhiyunOMAP 3 ISP Device Tree bindings 2*4882a593Smuzhiyun=============================== 3*4882a593Smuzhiyun 4*4882a593SmuzhiyunThe DT definitions can be found in include/dt-bindings/media/omap3-isp.h. 5*4882a593Smuzhiyun 6*4882a593SmuzhiyunRequired properties 7*4882a593Smuzhiyun=================== 8*4882a593Smuzhiyun 9*4882a593Smuzhiyuncompatible : must contain "ti,omap3-isp" 10*4882a593Smuzhiyun 11*4882a593Smuzhiyunreg : the two registers sets (physical address and length) for the 12*4882a593Smuzhiyun ISP. The first set contains the core ISP registers up to 13*4882a593Smuzhiyun the end of the SBL block. The second set contains the 14*4882a593Smuzhiyun CSI PHYs and receivers registers. 15*4882a593Smuzhiyuninterrupts : the ISP interrupt specifier 16*4882a593Smuzhiyuniommus : phandle and IOMMU specifier for the IOMMU that serves the ISP 17*4882a593Smuzhiyunsyscon : the phandle and register offset to the Complex I/O or CSI-PHY 18*4882a593Smuzhiyun register 19*4882a593Smuzhiyunti,phy-type : 0 -- OMAP3ISP_PHY_TYPE_COMPLEX_IO (e.g. 3430) 20*4882a593Smuzhiyun 1 -- OMAP3ISP_PHY_TYPE_CSIPHY (e.g. 3630) 21*4882a593Smuzhiyun#clock-cells : Must be 1 --- the ISP provides two external clocks, 22*4882a593Smuzhiyun cam_xclka and cam_xclkb, at indices 0 and 1, 23*4882a593Smuzhiyun respectively. Please find more information on common 24*4882a593Smuzhiyun clock bindings in ../clock/clock-bindings.txt. 25*4882a593Smuzhiyun 26*4882a593SmuzhiyunPort nodes (optional) 27*4882a593Smuzhiyun--------------------- 28*4882a593Smuzhiyun 29*4882a593SmuzhiyunMore documentation on these bindings is available in 30*4882a593Smuzhiyunvideo-interfaces.txt in the same directory. 31*4882a593Smuzhiyun 32*4882a593Smuzhiyunreg : The interface: 33*4882a593Smuzhiyun 0 - parallel (CCDC) 34*4882a593Smuzhiyun 1 - CSIPHY1 -- CSI2C / CCP2B on 3630; 35*4882a593Smuzhiyun CSI1 -- CSIb on 3430 36*4882a593Smuzhiyun 2 - CSIPHY2 -- CSI2A / CCP2B on 3630; 37*4882a593Smuzhiyun CSI2 -- CSIa on 3430 38*4882a593Smuzhiyun 39*4882a593SmuzhiyunOptional properties 40*4882a593Smuzhiyun=================== 41*4882a593Smuzhiyun 42*4882a593Smuzhiyunvdd-csiphy1-supply : voltage supply of the CSI-2 PHY 1 43*4882a593Smuzhiyunvdd-csiphy2-supply : voltage supply of the CSI-2 PHY 2 44*4882a593Smuzhiyun 45*4882a593SmuzhiyunEndpoint nodes 46*4882a593Smuzhiyun-------------- 47*4882a593Smuzhiyun 48*4882a593Smuzhiyunlane-polarities : lane polarity (required on CSI-2) 49*4882a593Smuzhiyun 0 -- not inverted; 1 -- inverted 50*4882a593Smuzhiyundata-lanes : an array of data lanes from 1 to 3. The length can 51*4882a593Smuzhiyun be either 1 or 2. (required on CSI-2) 52*4882a593Smuzhiyunclock-lanes : the clock lane (from 1 to 3). (required on CSI-2) 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun 55*4882a593SmuzhiyunExample 56*4882a593Smuzhiyun======= 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun isp@480bc000 { 59*4882a593Smuzhiyun compatible = "ti,omap3-isp"; 60*4882a593Smuzhiyun reg = <0x480bc000 0x12fc 61*4882a593Smuzhiyun 0x480bd800 0x0600>; 62*4882a593Smuzhiyun interrupts = <24>; 63*4882a593Smuzhiyun iommus = <&mmu_isp>; 64*4882a593Smuzhiyun syscon = <&scm_conf 0x2f0>; 65*4882a593Smuzhiyun ti,phy-type = <OMAP3ISP_PHY_TYPE_CSIPHY>; 66*4882a593Smuzhiyun #clock-cells = <1>; 67*4882a593Smuzhiyun ports { 68*4882a593Smuzhiyun #address-cells = <1>; 69*4882a593Smuzhiyun #size-cells = <0>; 70*4882a593Smuzhiyun }; 71*4882a593Smuzhiyun }; 72