1*4882a593SmuzhiyunTexas Instruments VPIF 2*4882a593Smuzhiyun---------------------- 3*4882a593Smuzhiyun 4*4882a593SmuzhiyunThe TI Video Port InterFace (VPIF) is the primary component for video 5*4882a593Smuzhiyuncapture and display on the DA850/AM18x family of TI DaVinci/Sitara 6*4882a593SmuzhiyunSoCs. 7*4882a593Smuzhiyun 8*4882a593SmuzhiyunTI Document reference: SPRUH82C, Chapter 35 9*4882a593Smuzhiyunhttp://www.ti.com/lit/pdf/spruh82 10*4882a593Smuzhiyun 11*4882a593SmuzhiyunRequired properties: 12*4882a593Smuzhiyun- compatible: must be "ti,da850-vpif" 13*4882a593Smuzhiyun- reg: physical base address and length of the registers set for the device; 14*4882a593Smuzhiyun- interrupts: should contain IRQ line for the VPIF 15*4882a593Smuzhiyun 16*4882a593SmuzhiyunVideo Capture: 17*4882a593Smuzhiyun 18*4882a593SmuzhiyunVPIF has a 16-bit parallel bus input, supporting 2 8-bit channels or a 19*4882a593Smuzhiyunsingle 16-bit channel. It should contain one or two port child nodes 20*4882a593Smuzhiyunwith child 'endpoint' node. If there are two ports then port@0 must 21*4882a593Smuzhiyundescribe the input and port@1 output channels. Please refer to the 22*4882a593Smuzhiyunbindings defined in 23*4882a593SmuzhiyunDocumentation/devicetree/bindings/media/video-interfaces.txt. 24*4882a593Smuzhiyun 25*4882a593SmuzhiyunExample using 2 8-bit input channels, one of which is connected to an 26*4882a593SmuzhiyunI2C-connected TVP5147 decoder: 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun vpif: vpif@217000 { 29*4882a593Smuzhiyun compatible = "ti,da850-vpif"; 30*4882a593Smuzhiyun reg = <0x217000 0x1000>; 31*4882a593Smuzhiyun interrupts = <92>; 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun port@0 { 34*4882a593Smuzhiyun vpif_input_ch0: endpoint@0 { 35*4882a593Smuzhiyun reg = <0>; 36*4882a593Smuzhiyun bus-width = <8>; 37*4882a593Smuzhiyun remote-endpoint = <&composite_in>; 38*4882a593Smuzhiyun }; 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun vpif_input_ch1: endpoint@1 { 41*4882a593Smuzhiyun reg = <1>; 42*4882a593Smuzhiyun bus-width = <8>; 43*4882a593Smuzhiyun data-shift = <8>; 44*4882a593Smuzhiyun }; 45*4882a593Smuzhiyun }; 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun port@1 { 48*4882a593Smuzhiyun vpif_output_ch0: endpoint { 49*4882a593Smuzhiyun bus-width = <8>; 50*4882a593Smuzhiyun remote-endpoint = <&composite_out>; 51*4882a593Smuzhiyun }; 52*4882a593Smuzhiyun }; 53*4882a593Smuzhiyun }; 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun[ ... ] 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun&i2c0 { 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun tvp5147@5d { 60*4882a593Smuzhiyun compatible = "ti,tvp5147"; 61*4882a593Smuzhiyun reg = <0x5d>; 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun port { 64*4882a593Smuzhiyun composite_in: endpoint { 65*4882a593Smuzhiyun hsync-active = <1>; 66*4882a593Smuzhiyun vsync-active = <1>; 67*4882a593Smuzhiyun pclk-sample = <0>; 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun /* VPIF channel 0 (lower 8-bits) */ 70*4882a593Smuzhiyun remote-endpoint = <&vpif_input_ch0>; 71*4882a593Smuzhiyun bus-width = <8>; 72*4882a593Smuzhiyun }; 73*4882a593Smuzhiyun }; 74*4882a593Smuzhiyun }; 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun adv7343@2a { 77*4882a593Smuzhiyun compatible = "adi,adv7343"; 78*4882a593Smuzhiyun reg = <0x2a>; 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun port { 81*4882a593Smuzhiyun composite_out: endpoint { 82*4882a593Smuzhiyun adi,dac-enable = <1 1 1>; 83*4882a593Smuzhiyun adi,sd-dac-enable = <1>; 84*4882a593Smuzhiyun 85*4882a593Smuzhiyun remote-endpoint = <&vpif_output_ch0>; 86*4882a593Smuzhiyun bus-width = <8>; 87*4882a593Smuzhiyun }; 88*4882a593Smuzhiyun }; 89*4882a593Smuzhiyun }; 90*4882a593Smuzhiyun}; 91*4882a593Smuzhiyun 92*4882a593Smuzhiyun 93*4882a593SmuzhiyunAlternatively, an example when the bus is configured as a single 94*4882a593Smuzhiyun16-bit input (e.g. for raw-capture mode): 95*4882a593Smuzhiyun 96*4882a593Smuzhiyun vpif: vpif@217000 { 97*4882a593Smuzhiyun compatible = "ti,da850-vpif"; 98*4882a593Smuzhiyun reg = <0x217000 0x1000>; 99*4882a593Smuzhiyun interrupts = <92>; 100*4882a593Smuzhiyun 101*4882a593Smuzhiyun port { 102*4882a593Smuzhiyun vpif_ch0: endpoint { 103*4882a593Smuzhiyun bus-width = <16>; 104*4882a593Smuzhiyun }; 105*4882a593Smuzhiyun }; 106*4882a593Smuzhiyun }; 107