1*4882a593SmuzhiyunSTMicroelectronics STi c8sectpfe binding 2*4882a593Smuzhiyun============================================ 3*4882a593Smuzhiyun 4*4882a593SmuzhiyunThis document describes the c8sectpfe device bindings that is used to get transport 5*4882a593Smuzhiyunstream data into the SoC on the TS pins, and into DDR for further processing. 6*4882a593Smuzhiyun 7*4882a593SmuzhiyunIt is typically used in conjunction with one or more demodulator and tuner devices 8*4882a593Smuzhiyunwhich converts from the RF to digital domain. Demodulators and tuners are usually 9*4882a593Smuzhiyunlocated on an external DVB frontend card connected to SoC TS input pins. 10*4882a593Smuzhiyun 11*4882a593SmuzhiyunCurrently 7 TS input (tsin) channels are supported on the stih407 family SoC. 12*4882a593Smuzhiyun 13*4882a593SmuzhiyunRequired properties (controller (parent) node): 14*4882a593Smuzhiyun- compatible : Should be "stih407-c8sectpfe" 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun- reg : Address and length of register sets for each device in 17*4882a593Smuzhiyun "reg-names" 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun- reg-names : The names of the register addresses corresponding to the 20*4882a593Smuzhiyun registers filled in "reg": 21*4882a593Smuzhiyun - c8sectpfe: c8sectpfe registers 22*4882a593Smuzhiyun - c8sectpfe-ram: c8sectpfe internal sram 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun- clocks : phandle list of c8sectpfe clocks 25*4882a593Smuzhiyun- clock-names : should be "c8sectpfe" 26*4882a593SmuzhiyunSee: Documentation/devicetree/bindings/clock/clock-bindings.txt 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun- pinctrl-names : a pinctrl state named tsin%d-serial or tsin%d-parallel (where %d is tsin-num) 29*4882a593Smuzhiyun must be defined for each tsin child node. 30*4882a593Smuzhiyun- pinctrl-0 : phandle referencing pin configuration for this tsin configuration 31*4882a593SmuzhiyunSee: Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun 34*4882a593SmuzhiyunRequired properties (tsin (child) node): 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun- tsin-num : tsin id of the InputBlock (must be between 0 to 6) 37*4882a593Smuzhiyun- i2c-bus : phandle to the I2C bus DT node which the demodulators & tuners on this tsin channel are connected. 38*4882a593Smuzhiyun- reset-gpios : reset gpio for this tsin channel. 39*4882a593Smuzhiyun 40*4882a593SmuzhiyunOptional properties (tsin (child) node): 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun- invert-ts-clk : Bool property to control sense of ts input clock (data stored on falling edge of clk). 43*4882a593Smuzhiyun- serial-not-parallel : Bool property to configure input bus width (serial on ts_data<7>). 44*4882a593Smuzhiyun- async-not-sync : Bool property to control if data is received in asynchronous mode 45*4882a593Smuzhiyun (all bits/bytes with ts_valid or ts_packet asserted are valid). 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun- dvb-card : Describes the NIM card connected to this tsin channel. 48*4882a593Smuzhiyun 49*4882a593SmuzhiyunExample: 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun/* stih410 SoC b2120 + b2004a + stv0367-pll(NIMB) + stv0367-tda18212 (NIMA) DT example) */ 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun c8sectpfe@8a20000 { 54*4882a593Smuzhiyun compatible = "st,stih407-c8sectpfe"; 55*4882a593Smuzhiyun reg = <0x08a20000 0x10000>, <0x08a00000 0x4000>; 56*4882a593Smuzhiyun reg-names = "stfe", "stfe-ram"; 57*4882a593Smuzhiyun interrupts = <GIC_SPI 34 IRQ_TYPE_NONE>, <GIC_SPI 35 IRQ_TYPE_NONE>; 58*4882a593Smuzhiyun interrupt-names = "stfe-error-irq", "stfe-idle-irq"; 59*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_tsin0_serial>; 60*4882a593Smuzhiyun pinctrl-1 = <&pinctrl_tsin0_parallel>; 61*4882a593Smuzhiyun pinctrl-2 = <&pinctrl_tsin3_serial>; 62*4882a593Smuzhiyun pinctrl-3 = <&pinctrl_tsin4_serial_alt3>; 63*4882a593Smuzhiyun pinctrl-4 = <&pinctrl_tsin5_serial_alt1>; 64*4882a593Smuzhiyun pinctrl-names = "tsin0-serial", 65*4882a593Smuzhiyun "tsin0-parallel", 66*4882a593Smuzhiyun "tsin3-serial", 67*4882a593Smuzhiyun "tsin4-serial", 68*4882a593Smuzhiyun "tsin5-serial"; 69*4882a593Smuzhiyun clocks = <&clk_s_c0_flexgen CLK_PROC_STFE>; 70*4882a593Smuzhiyun clock-names = "c8sectpfe"; 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun /* tsin0 is TSA on NIMA */ 73*4882a593Smuzhiyun tsin0: port@0 { 74*4882a593Smuzhiyun tsin-num = <0>; 75*4882a593Smuzhiyun serial-not-parallel; 76*4882a593Smuzhiyun i2c-bus = <&ssc2>; 77*4882a593Smuzhiyun reset-gpios = <&pio15 4 GPIO_ACTIVE_HIGH>; 78*4882a593Smuzhiyun dvb-card = <STV0367_TDA18212_NIMA_1>; 79*4882a593Smuzhiyun }; 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun tsin3: port@3 { 82*4882a593Smuzhiyun tsin-num = <3>; 83*4882a593Smuzhiyun serial-not-parallel; 84*4882a593Smuzhiyun i2c-bus = <&ssc3>; 85*4882a593Smuzhiyun reset-gpios = <&pio15 7 GPIO_ACTIVE_HIGH>; 86*4882a593Smuzhiyun dvb-card = <STV0367_TDA18212_NIMB_1>; 87*4882a593Smuzhiyun }; 88*4882a593Smuzhiyun }; 89