1*4882a593Smuzhiyun# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*4882a593Smuzhiyun%YAML 1.2 3*4882a593Smuzhiyun--- 4*4882a593Smuzhiyun$id: http://devicetree.org/schemas/media/st,stm32-dcmi.yaml# 5*4882a593Smuzhiyun$schema: http://devicetree.org/meta-schemas/core.yaml# 6*4882a593Smuzhiyun 7*4882a593Smuzhiyuntitle: STMicroelectronics STM32 Digital Camera Memory Interface (DCMI) binding 8*4882a593Smuzhiyun 9*4882a593Smuzhiyunmaintainers: 10*4882a593Smuzhiyun - Hugues Fruchet <hugues.fruchet@st.com> 11*4882a593Smuzhiyun 12*4882a593Smuzhiyunproperties: 13*4882a593Smuzhiyun compatible: 14*4882a593Smuzhiyun const: st,stm32-dcmi 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun reg: 17*4882a593Smuzhiyun maxItems: 1 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun interrupts: 20*4882a593Smuzhiyun maxItems: 1 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun clocks: 23*4882a593Smuzhiyun maxItems: 1 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun clock-names: 26*4882a593Smuzhiyun items: 27*4882a593Smuzhiyun - const: mclk 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun dmas: 30*4882a593Smuzhiyun maxItems: 1 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun dma-names: 33*4882a593Smuzhiyun items: 34*4882a593Smuzhiyun - const: tx 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun resets: 37*4882a593Smuzhiyun maxItems: 1 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun port: 40*4882a593Smuzhiyun type: object 41*4882a593Smuzhiyun description: 42*4882a593Smuzhiyun DCMI supports a single port node with parallel bus. It should contain 43*4882a593Smuzhiyun one 'port' child node with child 'endpoint' node. Please refer to the 44*4882a593Smuzhiyun bindings defined in 45*4882a593Smuzhiyun Documentation/devicetree/bindings/media/video-interfaces.txt. 46*4882a593Smuzhiyun 47*4882a593Smuzhiyunrequired: 48*4882a593Smuzhiyun - compatible 49*4882a593Smuzhiyun - reg 50*4882a593Smuzhiyun - interrupts 51*4882a593Smuzhiyun - clocks 52*4882a593Smuzhiyun - clock-names 53*4882a593Smuzhiyun - resets 54*4882a593Smuzhiyun - dmas 55*4882a593Smuzhiyun - dma-names 56*4882a593Smuzhiyun - port 57*4882a593Smuzhiyun 58*4882a593SmuzhiyunadditionalProperties: false 59*4882a593Smuzhiyun 60*4882a593Smuzhiyunexamples: 61*4882a593Smuzhiyun - | 62*4882a593Smuzhiyun #include <dt-bindings/interrupt-controller/arm-gic.h> 63*4882a593Smuzhiyun #include <dt-bindings/clock/stm32mp1-clks.h> 64*4882a593Smuzhiyun #include <dt-bindings/reset/stm32mp1-resets.h> 65*4882a593Smuzhiyun dcmi: dcmi@4c006000 { 66*4882a593Smuzhiyun compatible = "st,stm32-dcmi"; 67*4882a593Smuzhiyun reg = <0x4c006000 0x400>; 68*4882a593Smuzhiyun interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 69*4882a593Smuzhiyun resets = <&rcc CAMITF_R>; 70*4882a593Smuzhiyun clocks = <&rcc DCMI>; 71*4882a593Smuzhiyun clock-names = "mclk"; 72*4882a593Smuzhiyun dmas = <&dmamux1 75 0x400 0x0d>; 73*4882a593Smuzhiyun dma-names = "tx"; 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun port { 76*4882a593Smuzhiyun dcmi_0: endpoint { 77*4882a593Smuzhiyun remote-endpoint = <&ov5640_0>; 78*4882a593Smuzhiyun bus-width = <8>; 79*4882a593Smuzhiyun hsync-active = <0>; 80*4882a593Smuzhiyun vsync-active = <0>; 81*4882a593Smuzhiyun pclk-sample = <1>; 82*4882a593Smuzhiyun }; 83*4882a593Smuzhiyun }; 84*4882a593Smuzhiyun }; 85*4882a593Smuzhiyun 86*4882a593Smuzhiyun... 87