1*4882a593SmuzhiyunSamsung S5P/Exynos SoC series MIPI CSI-2 receiver (MIPI CSIS) 2*4882a593Smuzhiyun------------------------------------------------------------- 3*4882a593Smuzhiyun 4*4882a593SmuzhiyunRequired properties: 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun- compatible : "samsung,s5pv210-csis" for S5PV210 (S5PC110), 7*4882a593Smuzhiyun "samsung,exynos4210-csis" for Exynos4210 (S5PC210), 8*4882a593Smuzhiyun "samsung,exynos4212-csis" for Exynos4212/Exynos4412, 9*4882a593Smuzhiyun "samsung,exynos5250-csis" for Exynos5250; 10*4882a593Smuzhiyun- reg : offset and length of the register set for the device; 11*4882a593Smuzhiyun- interrupts : should contain MIPI CSIS interrupt; the format of the 12*4882a593Smuzhiyun interrupt specifier depends on the interrupt controller; 13*4882a593Smuzhiyun- bus-width : maximum number of data lanes supported (SoC specific); 14*4882a593Smuzhiyun- vddio-supply : MIPI CSIS I/O and PLL voltage supply (e.g. 1.8V); 15*4882a593Smuzhiyun- vddcore-supply : MIPI CSIS Core voltage supply (e.g. 1.1V); 16*4882a593Smuzhiyun- clocks : list of clock specifiers, corresponding to entries in 17*4882a593Smuzhiyun clock-names property; 18*4882a593Smuzhiyun- clock-names : must contain "csis", "sclk_csis" entries, matching entries 19*4882a593Smuzhiyun in the clocks property. 20*4882a593Smuzhiyun 21*4882a593SmuzhiyunOptional properties: 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun- clock-frequency : The IP's main (system bus) clock frequency in Hz, default 24*4882a593Smuzhiyun value when this property is not specified is 166 MHz; 25*4882a593Smuzhiyun- samsung,csis-wclk : CSI-2 wrapper clock selection. If this property is present 26*4882a593Smuzhiyun external clock from CMU will be used, or the bus clock if 27*4882a593Smuzhiyun if it's not specified. 28*4882a593Smuzhiyun 29*4882a593SmuzhiyunThe device node should contain one 'port' child node with one child 'endpoint' 30*4882a593Smuzhiyunnode, according to the bindings defined in Documentation/devicetree/bindings/ 31*4882a593Smuzhiyunmedia/video-interfaces.txt. The following are properties specific to those nodes. 32*4882a593Smuzhiyun 33*4882a593Smuzhiyunport node 34*4882a593Smuzhiyun--------- 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun- reg : (required) must be 3 for camera C input (CSIS0) or 4 for 37*4882a593Smuzhiyun camera D input (CSIS1); 38*4882a593Smuzhiyun 39*4882a593Smuzhiyunendpoint node 40*4882a593Smuzhiyun------------- 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun- data-lanes : (required) an array specifying active physical MIPI-CSI2 43*4882a593Smuzhiyun data input lanes and their mapping to logical lanes; the 44*4882a593Smuzhiyun array's content is unused, only its length is meaningful; 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun- samsung,csis-hs-settle : (optional) differential receiver (HS-RX) settle time; 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun 49*4882a593SmuzhiyunExample: 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun reg0: regulator@0 { 52*4882a593Smuzhiyun }; 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun reg1: regulator@1 { 55*4882a593Smuzhiyun }; 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun/* SoC properties */ 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun csis_0: csis@11880000 { 60*4882a593Smuzhiyun compatible = "samsung,exynos4210-csis"; 61*4882a593Smuzhiyun reg = <0x11880000 0x1000>; 62*4882a593Smuzhiyun interrupts = <0 78 0>; 63*4882a593Smuzhiyun #address-cells = <1>; 64*4882a593Smuzhiyun #size-cells = <0>; 65*4882a593Smuzhiyun }; 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun/* Board properties */ 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun csis_0: csis@11880000 { 70*4882a593Smuzhiyun clock-frequency = <166000000>; 71*4882a593Smuzhiyun vddio-supply = <®0>; 72*4882a593Smuzhiyun vddcore-supply = <®1>; 73*4882a593Smuzhiyun port { 74*4882a593Smuzhiyun reg = <3>; /* 3 - CSIS0, 4 - CSIS1 */ 75*4882a593Smuzhiyun csis0_ep: endpoint { 76*4882a593Smuzhiyun remote-endpoint = <...>; 77*4882a593Smuzhiyun data-lanes = <1>, <2>; 78*4882a593Smuzhiyun samsung,csis-hs-settle = <12>; 79*4882a593Smuzhiyun }; 80*4882a593Smuzhiyun }; 81*4882a593Smuzhiyun }; 82