1*4882a593Smuzhiyun# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 2*4882a593Smuzhiyun 3*4882a593Smuzhiyun%YAML 1.2 4*4882a593Smuzhiyun--- 5*4882a593Smuzhiyun$id: "http://devicetree.org/schemas/media/rockchip-vpu.yaml#" 6*4882a593Smuzhiyun$schema: "http://devicetree.org/meta-schemas/core.yaml#" 7*4882a593Smuzhiyun 8*4882a593Smuzhiyuntitle: Hantro G1 VPU codecs implemented on Rockchip SoCs 9*4882a593Smuzhiyun 10*4882a593Smuzhiyunmaintainers: 11*4882a593Smuzhiyun - Ezequiel Garcia <ezequiel@collabora.com> 12*4882a593Smuzhiyun 13*4882a593Smuzhiyundescription: 14*4882a593Smuzhiyun Hantro G1 video encode and decode accelerators present on Rockchip SoCs. 15*4882a593Smuzhiyun 16*4882a593Smuzhiyunproperties: 17*4882a593Smuzhiyun compatible: 18*4882a593Smuzhiyun enum: 19*4882a593Smuzhiyun - rockchip,rk3288-vpu 20*4882a593Smuzhiyun - rockchip,rk3328-vpu 21*4882a593Smuzhiyun - rockchip,rk3399-vpu 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun reg: 24*4882a593Smuzhiyun maxItems: 1 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun interrupts: 27*4882a593Smuzhiyun minItems: 1 28*4882a593Smuzhiyun maxItems: 2 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun interrupt-names: 31*4882a593Smuzhiyun oneOf: 32*4882a593Smuzhiyun - const: vdpu 33*4882a593Smuzhiyun - items: 34*4882a593Smuzhiyun - const: vepu 35*4882a593Smuzhiyun - const: vdpu 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun clocks: 38*4882a593Smuzhiyun maxItems: 2 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun clock-names: 41*4882a593Smuzhiyun items: 42*4882a593Smuzhiyun - const: aclk 43*4882a593Smuzhiyun - const: hclk 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun power-domains: 46*4882a593Smuzhiyun maxItems: 1 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun iommus: 49*4882a593Smuzhiyun maxItems: 1 50*4882a593Smuzhiyun 51*4882a593Smuzhiyunrequired: 52*4882a593Smuzhiyun - compatible 53*4882a593Smuzhiyun - reg 54*4882a593Smuzhiyun - interrupts 55*4882a593Smuzhiyun - interrupt-names 56*4882a593Smuzhiyun - clocks 57*4882a593Smuzhiyun - clock-names 58*4882a593Smuzhiyun 59*4882a593SmuzhiyunadditionalProperties: false 60*4882a593Smuzhiyun 61*4882a593Smuzhiyunexamples: 62*4882a593Smuzhiyun - | 63*4882a593Smuzhiyun #include <dt-bindings/clock/rk3288-cru.h> 64*4882a593Smuzhiyun #include <dt-bindings/interrupt-controller/arm-gic.h> 65*4882a593Smuzhiyun #include <dt-bindings/power/rk3288-power.h> 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun vpu: video-codec@ff9a0000 { 68*4882a593Smuzhiyun compatible = "rockchip,rk3288-vpu"; 69*4882a593Smuzhiyun reg = <0xff9a0000 0x800>; 70*4882a593Smuzhiyun interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 71*4882a593Smuzhiyun <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 72*4882a593Smuzhiyun interrupt-names = "vepu", "vdpu"; 73*4882a593Smuzhiyun clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>; 74*4882a593Smuzhiyun clock-names = "aclk", "hclk"; 75*4882a593Smuzhiyun power-domains = <&power RK3288_PD_VIDEO>; 76*4882a593Smuzhiyun iommus = <&vpu_mmu>; 77*4882a593Smuzhiyun }; 78