1*4882a593Smuzhiyun# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 2*4882a593Smuzhiyun%YAML 1.2 3*4882a593Smuzhiyun--- 4*4882a593Smuzhiyun$id: http://devicetree.org/schemas/media/renesas,fdp1.yaml# 5*4882a593Smuzhiyun$schema: http://devicetree.org/meta-schemas/core.yaml# 6*4882a593Smuzhiyun 7*4882a593Smuzhiyuntitle: Renesas R-Car Fine Display Processor (FDP1) 8*4882a593Smuzhiyun 9*4882a593Smuzhiyunmaintainers: 10*4882a593Smuzhiyun - Laurent Pinchart <laurent.pinchart@ideasonboard.com> 11*4882a593Smuzhiyun 12*4882a593Smuzhiyundescription: 13*4882a593Smuzhiyun The FDP1 is a de-interlacing module which converts interlaced video to 14*4882a593Smuzhiyun progressive video. It is capable of performing pixel format conversion 15*4882a593Smuzhiyun between YCbCr/YUV formats and RGB formats. Only YCbCr/YUV formats are 16*4882a593Smuzhiyun supported as an input to the module. 17*4882a593Smuzhiyun 18*4882a593Smuzhiyunproperties: 19*4882a593Smuzhiyun compatible: 20*4882a593Smuzhiyun enum: 21*4882a593Smuzhiyun - renesas,fdp1 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun reg: 24*4882a593Smuzhiyun maxItems: 1 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun interrupts: 27*4882a593Smuzhiyun maxItems: 1 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun clocks: 30*4882a593Smuzhiyun maxItems: 1 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun power-domains: 33*4882a593Smuzhiyun maxItems: 1 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun resets: 36*4882a593Smuzhiyun maxItems: 1 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun renesas,fcp: 39*4882a593Smuzhiyun $ref: /schemas/types.yaml#/definitions/phandle 40*4882a593Smuzhiyun description: 41*4882a593Smuzhiyun A phandle referencing the FCP that handles memory accesses for the FDP1. 42*4882a593Smuzhiyun Not allowed on R-Car Gen2, mandatory on R-Car Gen3. 43*4882a593Smuzhiyun 44*4882a593Smuzhiyunrequired: 45*4882a593Smuzhiyun - compatible 46*4882a593Smuzhiyun - reg 47*4882a593Smuzhiyun - interrupts 48*4882a593Smuzhiyun - clocks 49*4882a593Smuzhiyun - power-domains 50*4882a593Smuzhiyun - resets 51*4882a593Smuzhiyun 52*4882a593SmuzhiyunadditionalProperties: false 53*4882a593Smuzhiyun 54*4882a593Smuzhiyunexamples: 55*4882a593Smuzhiyun - | 56*4882a593Smuzhiyun #include <dt-bindings/clock/renesas-cpg-mssr.h> 57*4882a593Smuzhiyun #include <dt-bindings/interrupt-controller/arm-gic.h> 58*4882a593Smuzhiyun #include <dt-bindings/power/r8a7795-sysc.h> 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun fdp1@fe940000 { 61*4882a593Smuzhiyun compatible = "renesas,fdp1"; 62*4882a593Smuzhiyun reg = <0xfe940000 0x2400>; 63*4882a593Smuzhiyun interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>; 64*4882a593Smuzhiyun clocks = <&cpg CPG_MOD 119>; 65*4882a593Smuzhiyun power-domains = <&sysc R8A7795_PD_A3VP>; 66*4882a593Smuzhiyun resets = <&cpg 119>; 67*4882a593Smuzhiyun renesas,fcp = <&fcpf0>; 68*4882a593Smuzhiyun }; 69*4882a593Smuzhiyun... 70