1*4882a593Smuzhiyun* Renesas JPEG Processing Unit 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunThe JPEG processing unit (JPU) incorporates the JPEG codec with an encoding 4*4882a593Smuzhiyunand decoding function conforming to the JPEG baseline process, so that the JPU 5*4882a593Smuzhiyuncan encode image data and decode JPEG data quickly. 6*4882a593Smuzhiyun 7*4882a593SmuzhiyunRequired properties: 8*4882a593Smuzhiyun- compatible: "renesas,jpu-<soctype>", "renesas,rcar-gen2-jpu" as fallback. 9*4882a593Smuzhiyun Examples with soctypes are: 10*4882a593Smuzhiyun - "renesas,jpu-r8a7790" for R-Car H2 11*4882a593Smuzhiyun - "renesas,jpu-r8a7791" for R-Car M2-W 12*4882a593Smuzhiyun - "renesas,jpu-r8a7792" for R-Car V2H 13*4882a593Smuzhiyun - "renesas,jpu-r8a7793" for R-Car M2-N 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun - reg: Base address and length of the registers block for the JPU. 16*4882a593Smuzhiyun - interrupts: JPU interrupt specifier. 17*4882a593Smuzhiyun - clocks: A phandle + clock-specifier pair for the JPU functional clock. 18*4882a593Smuzhiyun 19*4882a593SmuzhiyunExample: R8A7790 (R-Car H2) JPU node 20*4882a593Smuzhiyun jpeg-codec@fe980000 { 21*4882a593Smuzhiyun compatible = "renesas,jpu-r8a7790", "renesas,rcar-gen2-jpu"; 22*4882a593Smuzhiyun reg = <0 0xfe980000 0 0x10300>; 23*4882a593Smuzhiyun interrupts = <0 272 IRQ_TYPE_LEVEL_HIGH>; 24*4882a593Smuzhiyun clocks = <&mstp1_clks R8A7790_CLK_JPU>; 25*4882a593Smuzhiyun }; 26