1*4882a593SmuzhiyunQualcomm Camera Subsystem 2*4882a593Smuzhiyun 3*4882a593Smuzhiyun* Properties 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun- compatible: 6*4882a593Smuzhiyun Usage: required 7*4882a593Smuzhiyun Value type: <stringlist> 8*4882a593Smuzhiyun Definition: Should contain one of: 9*4882a593Smuzhiyun - "qcom,msm8916-camss" 10*4882a593Smuzhiyun - "qcom,msm8996-camss" 11*4882a593Smuzhiyun- reg: 12*4882a593Smuzhiyun Usage: required 13*4882a593Smuzhiyun Value type: <prop-encoded-array> 14*4882a593Smuzhiyun Definition: Register ranges as listed in the reg-names property. 15*4882a593Smuzhiyun- reg-names: 16*4882a593Smuzhiyun Usage: required 17*4882a593Smuzhiyun Value type: <stringlist> 18*4882a593Smuzhiyun Definition: Should contain the following entries: 19*4882a593Smuzhiyun - "csiphy0" 20*4882a593Smuzhiyun - "csiphy0_clk_mux" 21*4882a593Smuzhiyun - "csiphy1" 22*4882a593Smuzhiyun - "csiphy1_clk_mux" 23*4882a593Smuzhiyun - "csiphy2" (8996 only) 24*4882a593Smuzhiyun - "csiphy2_clk_mux" (8996 only) 25*4882a593Smuzhiyun - "csid0" 26*4882a593Smuzhiyun - "csid1" 27*4882a593Smuzhiyun - "csid2" (8996 only) 28*4882a593Smuzhiyun - "csid3" (8996 only) 29*4882a593Smuzhiyun - "ispif" 30*4882a593Smuzhiyun - "csi_clk_mux" 31*4882a593Smuzhiyun - "vfe0" 32*4882a593Smuzhiyun - "vfe1" (8996 only) 33*4882a593Smuzhiyun- interrupts: 34*4882a593Smuzhiyun Usage: required 35*4882a593Smuzhiyun Value type: <prop-encoded-array> 36*4882a593Smuzhiyun Definition: Interrupts as listed in the interrupt-names property. 37*4882a593Smuzhiyun- interrupt-names: 38*4882a593Smuzhiyun Usage: required 39*4882a593Smuzhiyun Value type: <stringlist> 40*4882a593Smuzhiyun Definition: Should contain the following entries: 41*4882a593Smuzhiyun - "csiphy0" 42*4882a593Smuzhiyun - "csiphy1" 43*4882a593Smuzhiyun - "csiphy2" (8996 only) 44*4882a593Smuzhiyun - "csid0" 45*4882a593Smuzhiyun - "csid1" 46*4882a593Smuzhiyun - "csid2" (8996 only) 47*4882a593Smuzhiyun - "csid3" (8996 only) 48*4882a593Smuzhiyun - "ispif" 49*4882a593Smuzhiyun - "vfe0" 50*4882a593Smuzhiyun - "vfe1" (8996 only) 51*4882a593Smuzhiyun- power-domains: 52*4882a593Smuzhiyun Usage: required 53*4882a593Smuzhiyun Value type: <prop-encoded-array> 54*4882a593Smuzhiyun Definition: A phandle and power domain specifier pairs to the 55*4882a593Smuzhiyun power domain which is responsible for collapsing 56*4882a593Smuzhiyun and restoring power to the peripheral. 57*4882a593Smuzhiyun- clocks: 58*4882a593Smuzhiyun Usage: required 59*4882a593Smuzhiyun Value type: <prop-encoded-array> 60*4882a593Smuzhiyun Definition: A list of phandle and clock specifier pairs as listed 61*4882a593Smuzhiyun in clock-names property. 62*4882a593Smuzhiyun- clock-names: 63*4882a593Smuzhiyun Usage: required 64*4882a593Smuzhiyun Value type: <stringlist> 65*4882a593Smuzhiyun Definition: Should contain the following entries: 66*4882a593Smuzhiyun - "top_ahb" 67*4882a593Smuzhiyun - "ispif_ahb" 68*4882a593Smuzhiyun - "csiphy0_timer" 69*4882a593Smuzhiyun - "csiphy1_timer" 70*4882a593Smuzhiyun - "csiphy2_timer" (8996 only) 71*4882a593Smuzhiyun - "csi0_ahb" 72*4882a593Smuzhiyun - "csi0" 73*4882a593Smuzhiyun - "csi0_phy" 74*4882a593Smuzhiyun - "csi0_pix" 75*4882a593Smuzhiyun - "csi0_rdi" 76*4882a593Smuzhiyun - "csi1_ahb" 77*4882a593Smuzhiyun - "csi1" 78*4882a593Smuzhiyun - "csi1_phy" 79*4882a593Smuzhiyun - "csi1_pix" 80*4882a593Smuzhiyun - "csi1_rdi" 81*4882a593Smuzhiyun - "csi2_ahb" (8996 only) 82*4882a593Smuzhiyun - "csi2" (8996 only) 83*4882a593Smuzhiyun - "csi2_phy" (8996 only) 84*4882a593Smuzhiyun - "csi2_pix" (8996 only) 85*4882a593Smuzhiyun - "csi2_rdi" (8996 only) 86*4882a593Smuzhiyun - "csi3_ahb" (8996 only) 87*4882a593Smuzhiyun - "csi3" (8996 only) 88*4882a593Smuzhiyun - "csi3_phy" (8996 only) 89*4882a593Smuzhiyun - "csi3_pix" (8996 only) 90*4882a593Smuzhiyun - "csi3_rdi" (8996 only) 91*4882a593Smuzhiyun - "ahb" 92*4882a593Smuzhiyun - "vfe0" 93*4882a593Smuzhiyun - "csi_vfe0" 94*4882a593Smuzhiyun - "vfe0_ahb", (8996 only) 95*4882a593Smuzhiyun - "vfe0_stream", (8996 only) 96*4882a593Smuzhiyun - "vfe1", (8996 only) 97*4882a593Smuzhiyun - "csi_vfe1", (8996 only) 98*4882a593Smuzhiyun - "vfe1_ahb", (8996 only) 99*4882a593Smuzhiyun - "vfe1_stream", (8996 only) 100*4882a593Smuzhiyun - "vfe_ahb" 101*4882a593Smuzhiyun - "vfe_axi" 102*4882a593Smuzhiyun- vdda-supply: 103*4882a593Smuzhiyun Usage: required 104*4882a593Smuzhiyun Value type: <phandle> 105*4882a593Smuzhiyun Definition: A phandle to voltage supply for CSI2. 106*4882a593Smuzhiyun- iommus: 107*4882a593Smuzhiyun Usage: required 108*4882a593Smuzhiyun Value type: <prop-encoded-array> 109*4882a593Smuzhiyun Definition: A list of phandle and IOMMU specifier pairs. 110*4882a593Smuzhiyun 111*4882a593Smuzhiyun* Nodes 112*4882a593Smuzhiyun 113*4882a593Smuzhiyun- ports: 114*4882a593Smuzhiyun Usage: required 115*4882a593Smuzhiyun Definition: As described in video-interfaces.txt in same directory. 116*4882a593Smuzhiyun Properties: 117*4882a593Smuzhiyun - reg: 118*4882a593Smuzhiyun Usage: required 119*4882a593Smuzhiyun Value type: <u32> 120*4882a593Smuzhiyun Definition: Selects CSI2 PHY interface - PHY0, PHY1 121*4882a593Smuzhiyun or PHY2 (8996 only) 122*4882a593Smuzhiyun Endpoint node properties: 123*4882a593Smuzhiyun - clock-lanes: 124*4882a593Smuzhiyun Usage: required 125*4882a593Smuzhiyun Value type: <u32> 126*4882a593Smuzhiyun Definition: The physical clock lane index. On 8916 127*4882a593Smuzhiyun the value must always be <1> as the physical 128*4882a593Smuzhiyun clock lane is lane 1. On 8996 the value must 129*4882a593Smuzhiyun always be <7> as the hardware supports D-PHY 130*4882a593Smuzhiyun and C-PHY, indexes are in a common set and 131*4882a593Smuzhiyun D-PHY physical clock lane is labeled as 7. 132*4882a593Smuzhiyun - data-lanes: 133*4882a593Smuzhiyun Usage: required 134*4882a593Smuzhiyun Value type: <prop-encoded-array> 135*4882a593Smuzhiyun Definition: An array of physical data lanes indexes. 136*4882a593Smuzhiyun Position of an entry determines the logical 137*4882a593Smuzhiyun lane number, while the value of an entry 138*4882a593Smuzhiyun indicates physical lane index. Lane swapping 139*4882a593Smuzhiyun is supported. Physical lane indexes for 140*4882a593Smuzhiyun 8916: 0, 2, 3, 4; for 8996: 0, 1, 2, 3. 141*4882a593Smuzhiyun 142*4882a593Smuzhiyun* An Example 143*4882a593Smuzhiyun 144*4882a593Smuzhiyun camss: camss@1b00000 { 145*4882a593Smuzhiyun compatible = "qcom,msm8916-camss"; 146*4882a593Smuzhiyun reg = <0x1b0ac00 0x200>, 147*4882a593Smuzhiyun <0x1b00030 0x4>, 148*4882a593Smuzhiyun <0x1b0b000 0x200>, 149*4882a593Smuzhiyun <0x1b00038 0x4>, 150*4882a593Smuzhiyun <0x1b08000 0x100>, 151*4882a593Smuzhiyun <0x1b08400 0x100>, 152*4882a593Smuzhiyun <0x1b0a000 0x500>, 153*4882a593Smuzhiyun <0x1b00020 0x10>, 154*4882a593Smuzhiyun <0x1b10000 0x1000>; 155*4882a593Smuzhiyun reg-names = "csiphy0", 156*4882a593Smuzhiyun "csiphy0_clk_mux", 157*4882a593Smuzhiyun "csiphy1", 158*4882a593Smuzhiyun "csiphy1_clk_mux", 159*4882a593Smuzhiyun "csid0", 160*4882a593Smuzhiyun "csid1", 161*4882a593Smuzhiyun "ispif", 162*4882a593Smuzhiyun "csi_clk_mux", 163*4882a593Smuzhiyun "vfe0"; 164*4882a593Smuzhiyun interrupts = <GIC_SPI 78 0>, 165*4882a593Smuzhiyun <GIC_SPI 79 0>, 166*4882a593Smuzhiyun <GIC_SPI 51 0>, 167*4882a593Smuzhiyun <GIC_SPI 52 0>, 168*4882a593Smuzhiyun <GIC_SPI 55 0>, 169*4882a593Smuzhiyun <GIC_SPI 57 0>; 170*4882a593Smuzhiyun interrupt-names = "csiphy0", 171*4882a593Smuzhiyun "csiphy1", 172*4882a593Smuzhiyun "csid0", 173*4882a593Smuzhiyun "csid1", 174*4882a593Smuzhiyun "ispif", 175*4882a593Smuzhiyun "vfe0"; 176*4882a593Smuzhiyun power-domains = <&gcc VFE_GDSC>; 177*4882a593Smuzhiyun clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>, 178*4882a593Smuzhiyun <&gcc GCC_CAMSS_ISPIF_AHB_CLK>, 179*4882a593Smuzhiyun <&gcc GCC_CAMSS_CSI0PHYTIMER_CLK>, 180*4882a593Smuzhiyun <&gcc GCC_CAMSS_CSI1PHYTIMER_CLK>, 181*4882a593Smuzhiyun <&gcc GCC_CAMSS_CSI0_AHB_CLK>, 182*4882a593Smuzhiyun <&gcc GCC_CAMSS_CSI0_CLK>, 183*4882a593Smuzhiyun <&gcc GCC_CAMSS_CSI0PHY_CLK>, 184*4882a593Smuzhiyun <&gcc GCC_CAMSS_CSI0PIX_CLK>, 185*4882a593Smuzhiyun <&gcc GCC_CAMSS_CSI0RDI_CLK>, 186*4882a593Smuzhiyun <&gcc GCC_CAMSS_CSI1_AHB_CLK>, 187*4882a593Smuzhiyun <&gcc GCC_CAMSS_CSI1_CLK>, 188*4882a593Smuzhiyun <&gcc GCC_CAMSS_CSI1PHY_CLK>, 189*4882a593Smuzhiyun <&gcc GCC_CAMSS_CSI1PIX_CLK>, 190*4882a593Smuzhiyun <&gcc GCC_CAMSS_CSI1RDI_CLK>, 191*4882a593Smuzhiyun <&gcc GCC_CAMSS_AHB_CLK>, 192*4882a593Smuzhiyun <&gcc GCC_CAMSS_VFE0_CLK>, 193*4882a593Smuzhiyun <&gcc GCC_CAMSS_CSI_VFE0_CLK>, 194*4882a593Smuzhiyun <&gcc GCC_CAMSS_VFE_AHB_CLK>, 195*4882a593Smuzhiyun <&gcc GCC_CAMSS_VFE_AXI_CLK>; 196*4882a593Smuzhiyun clock-names = "top_ahb", 197*4882a593Smuzhiyun "ispif_ahb", 198*4882a593Smuzhiyun "csiphy0_timer", 199*4882a593Smuzhiyun "csiphy1_timer", 200*4882a593Smuzhiyun "csi0_ahb", 201*4882a593Smuzhiyun "csi0", 202*4882a593Smuzhiyun "csi0_phy", 203*4882a593Smuzhiyun "csi0_pix", 204*4882a593Smuzhiyun "csi0_rdi", 205*4882a593Smuzhiyun "csi1_ahb", 206*4882a593Smuzhiyun "csi1", 207*4882a593Smuzhiyun "csi1_phy", 208*4882a593Smuzhiyun "csi1_pix", 209*4882a593Smuzhiyun "csi1_rdi", 210*4882a593Smuzhiyun "ahb", 211*4882a593Smuzhiyun "vfe0", 212*4882a593Smuzhiyun "csi_vfe0", 213*4882a593Smuzhiyun "vfe_ahb", 214*4882a593Smuzhiyun "vfe_axi"; 215*4882a593Smuzhiyun vdda-supply = <&pm8916_l2>; 216*4882a593Smuzhiyun iommus = <&apps_iommu 3>; 217*4882a593Smuzhiyun ports { 218*4882a593Smuzhiyun #address-cells = <1>; 219*4882a593Smuzhiyun #size-cells = <0>; 220*4882a593Smuzhiyun port@0 { 221*4882a593Smuzhiyun reg = <0>; 222*4882a593Smuzhiyun csiphy0_ep: endpoint { 223*4882a593Smuzhiyun clock-lanes = <1>; 224*4882a593Smuzhiyun data-lanes = <0 2>; 225*4882a593Smuzhiyun remote-endpoint = <&ov5645_ep>; 226*4882a593Smuzhiyun }; 227*4882a593Smuzhiyun }; 228*4882a593Smuzhiyun }; 229*4882a593Smuzhiyun }; 230