1*4882a593SmuzhiyunMarvell PXA camera host interface 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunRequired properties: 4*4882a593Smuzhiyun - compatible: Should be "marvell,pxa270-qci" 5*4882a593Smuzhiyun - reg: register base and size 6*4882a593Smuzhiyun - interrupts: the interrupt number 7*4882a593Smuzhiyun - any required generic properties defined in video-interfaces.txt 8*4882a593Smuzhiyun 9*4882a593SmuzhiyunOptional properties: 10*4882a593Smuzhiyun - clocks: input clock (see clock-bindings.txt) 11*4882a593Smuzhiyun - clock-output-names: should contain the name of the clock driving the 12*4882a593Smuzhiyun sensor master clock MCLK 13*4882a593Smuzhiyun - clock-frequency: host interface is driving MCLK, and MCLK rate is this rate 14*4882a593Smuzhiyun 15*4882a593SmuzhiyunExample: 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun pxa_camera: pxa_camera@50000000 { 18*4882a593Smuzhiyun compatible = "marvell,pxa270-qci"; 19*4882a593Smuzhiyun reg = <0x50000000 0x1000>; 20*4882a593Smuzhiyun interrupts = <33>; 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun clocks = <&pxa2xx_clks 24>; 23*4882a593Smuzhiyun clock-names = "ciclk"; 24*4882a593Smuzhiyun clock-frequency = <50000000>; 25*4882a593Smuzhiyun clock-output-names = "qci_mclk"; 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun port { 29*4882a593Smuzhiyun #address-cells = <1>; 30*4882a593Smuzhiyun #size-cells = <0>; 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun /* Parallel bus endpoint */ 33*4882a593Smuzhiyun qci: endpoint@0 { 34*4882a593Smuzhiyun reg = <0>; /* Local endpoint # */ 35*4882a593Smuzhiyun remote-endpoint = <&mt9m111_1>; 36*4882a593Smuzhiyun bus-width = <8>; /* Used data lines */ 37*4882a593Smuzhiyun hsync-active = <0>; /* Active low */ 38*4882a593Smuzhiyun vsync-active = <0>; /* Active low */ 39*4882a593Smuzhiyun pclk-sample = <1>; /* Rising */ 40*4882a593Smuzhiyun }; 41*4882a593Smuzhiyun }; 42*4882a593Smuzhiyun }; 43