xref: /OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/media/nxp,imx8mq-vpu.yaml (revision 4882a59341e53eb6f0b4789bf948001014eff981) 
1*4882a593Smuzhiyun# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2*4882a593Smuzhiyun
3*4882a593Smuzhiyun%YAML 1.2
4*4882a593Smuzhiyun---
5*4882a593Smuzhiyun$id: "http://devicetree.org/schemas/media/nxp,imx8mq-vpu.yaml#"
6*4882a593Smuzhiyun$schema: "http://devicetree.org/meta-schemas/core.yaml#"
7*4882a593Smuzhiyun
8*4882a593Smuzhiyuntitle: Hantro G1/G2 VPU codecs implemented on i.MX8MQ SoCs
9*4882a593Smuzhiyun
10*4882a593Smuzhiyunmaintainers:
11*4882a593Smuzhiyun  - Philipp Zabel <p.zabel@pengutronix.de>
12*4882a593Smuzhiyun
13*4882a593Smuzhiyundescription:
14*4882a593Smuzhiyun  Hantro G1/G2 video decode accelerators present on i.MX8MQ SoCs.
15*4882a593Smuzhiyun
16*4882a593Smuzhiyunproperties:
17*4882a593Smuzhiyun  compatible:
18*4882a593Smuzhiyun    const: nxp,imx8mq-vpu
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun  reg:
21*4882a593Smuzhiyun    maxItems: 3
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun  reg-names:
24*4882a593Smuzhiyun    items:
25*4882a593Smuzhiyun      - const: g1
26*4882a593Smuzhiyun      - const: g2
27*4882a593Smuzhiyun      - const: ctrl
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun  interrupts:
30*4882a593Smuzhiyun    maxItems: 2
31*4882a593Smuzhiyun
32*4882a593Smuzhiyun  interrupt-names:
33*4882a593Smuzhiyun    items:
34*4882a593Smuzhiyun      - const: g1
35*4882a593Smuzhiyun      - const: g2
36*4882a593Smuzhiyun
37*4882a593Smuzhiyun  clocks:
38*4882a593Smuzhiyun    maxItems: 3
39*4882a593Smuzhiyun
40*4882a593Smuzhiyun  clock-names:
41*4882a593Smuzhiyun    items:
42*4882a593Smuzhiyun      - const: g1
43*4882a593Smuzhiyun      - const: g2
44*4882a593Smuzhiyun      - const: bus
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun  power-domains:
47*4882a593Smuzhiyun    maxItems: 1
48*4882a593Smuzhiyun
49*4882a593Smuzhiyunrequired:
50*4882a593Smuzhiyun  - compatible
51*4882a593Smuzhiyun  - reg
52*4882a593Smuzhiyun  - reg-names
53*4882a593Smuzhiyun  - interrupts
54*4882a593Smuzhiyun  - interrupt-names
55*4882a593Smuzhiyun  - clocks
56*4882a593Smuzhiyun  - clock-names
57*4882a593Smuzhiyun
58*4882a593SmuzhiyunadditionalProperties: false
59*4882a593Smuzhiyun
60*4882a593Smuzhiyunexamples:
61*4882a593Smuzhiyun  - |
62*4882a593Smuzhiyun        #include <dt-bindings/clock/imx8mq-clock.h>
63*4882a593Smuzhiyun        #include <dt-bindings/interrupt-controller/arm-gic.h>
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun        vpu: video-codec@38300000 {
66*4882a593Smuzhiyun                compatible = "nxp,imx8mq-vpu";
67*4882a593Smuzhiyun                reg = <0x38300000 0x10000>,
68*4882a593Smuzhiyun                      <0x38310000 0x10000>,
69*4882a593Smuzhiyun                      <0x38320000 0x10000>;
70*4882a593Smuzhiyun                reg-names = "g1", "g2", "ctrl";
71*4882a593Smuzhiyun                interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
72*4882a593Smuzhiyun                             <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
73*4882a593Smuzhiyun                interrupt-names = "g1", "g2";
74*4882a593Smuzhiyun                clocks = <&clk IMX8MQ_CLK_VPU_G1_ROOT>,
75*4882a593Smuzhiyun                         <&clk IMX8MQ_CLK_VPU_G2_ROOT>,
76*4882a593Smuzhiyun                         <&clk IMX8MQ_CLK_VPU_DEC_ROOT>;
77*4882a593Smuzhiyun                clock-names = "g1", "g2", "bus";
78*4882a593Smuzhiyun                power-domains = <&pgc_vpu>;
79*4882a593Smuzhiyun        };
80