1*4882a593SmuzhiyunNVIDIA Tegra Video Decoder Engine 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunRequired properties: 4*4882a593Smuzhiyun- compatible : Must contain one of the following values: 5*4882a593Smuzhiyun - "nvidia,tegra20-vde" 6*4882a593Smuzhiyun - "nvidia,tegra30-vde" 7*4882a593Smuzhiyun - "nvidia,tegra114-vde" 8*4882a593Smuzhiyun - "nvidia,tegra124-vde" 9*4882a593Smuzhiyun - "nvidia,tegra132-vde" 10*4882a593Smuzhiyun- reg : Must contain an entry for each entry in reg-names. 11*4882a593Smuzhiyun- reg-names : Must include the following entries: 12*4882a593Smuzhiyun - sxe 13*4882a593Smuzhiyun - bsev 14*4882a593Smuzhiyun - mbe 15*4882a593Smuzhiyun - ppe 16*4882a593Smuzhiyun - mce 17*4882a593Smuzhiyun - tfe 18*4882a593Smuzhiyun - ppb 19*4882a593Smuzhiyun - vdma 20*4882a593Smuzhiyun - frameid 21*4882a593Smuzhiyun- iram : Must contain phandle to the mmio-sram device node that represents 22*4882a593Smuzhiyun IRAM region used by VDE. 23*4882a593Smuzhiyun- interrupts : Must contain an entry for each entry in interrupt-names. 24*4882a593Smuzhiyun- interrupt-names : Must include the following entries: 25*4882a593Smuzhiyun - sync-token 26*4882a593Smuzhiyun - bsev 27*4882a593Smuzhiyun - sxe 28*4882a593Smuzhiyun- clocks : Must include the following entries: 29*4882a593Smuzhiyun - vde 30*4882a593Smuzhiyun- resets : Must contain an entry for each entry in reset-names. 31*4882a593Smuzhiyun- reset-names : Should include the following entries: 32*4882a593Smuzhiyun - vde 33*4882a593Smuzhiyun 34*4882a593SmuzhiyunOptional properties: 35*4882a593Smuzhiyun- resets : Must contain an entry for each entry in reset-names. 36*4882a593Smuzhiyun- reset-names : Must include the following entries: 37*4882a593Smuzhiyun - mc 38*4882a593Smuzhiyun- iommus: Must contain phandle to the IOMMU device node. 39*4882a593Smuzhiyun 40*4882a593SmuzhiyunExample: 41*4882a593Smuzhiyun 42*4882a593Smuzhiyunvideo-codec@6001a000 { 43*4882a593Smuzhiyun compatible = "nvidia,tegra20-vde"; 44*4882a593Smuzhiyun reg = <0x6001a000 0x1000 /* Syntax Engine */ 45*4882a593Smuzhiyun 0x6001b000 0x1000 /* Video Bitstream Engine */ 46*4882a593Smuzhiyun 0x6001c000 0x100 /* Macroblock Engine */ 47*4882a593Smuzhiyun 0x6001c200 0x100 /* Post-processing Engine */ 48*4882a593Smuzhiyun 0x6001c400 0x100 /* Motion Compensation Engine */ 49*4882a593Smuzhiyun 0x6001c600 0x100 /* Transform Engine */ 50*4882a593Smuzhiyun 0x6001c800 0x100 /* Pixel prediction block */ 51*4882a593Smuzhiyun 0x6001ca00 0x100 /* Video DMA */ 52*4882a593Smuzhiyun 0x6001d800 0x300 /* Video frame controls */>; 53*4882a593Smuzhiyun reg-names = "sxe", "bsev", "mbe", "ppe", "mce", 54*4882a593Smuzhiyun "tfe", "ppb", "vdma", "frameid"; 55*4882a593Smuzhiyun iram = <&vde_pool>; /* IRAM region */ 56*4882a593Smuzhiyun interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, /* Sync token interrupt */ 57*4882a593Smuzhiyun <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, /* BSE-V interrupt */ 58*4882a593Smuzhiyun <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; /* SXE interrupt */ 59*4882a593Smuzhiyun interrupt-names = "sync-token", "bsev", "sxe"; 60*4882a593Smuzhiyun clocks = <&tegra_car TEGRA20_CLK_VDE>; 61*4882a593Smuzhiyun reset-names = "vde", "mc"; 62*4882a593Smuzhiyun resets = <&tegra_car 61>, <&mc TEGRA20_MC_RESET_VDE>; 63*4882a593Smuzhiyun iommus = <&mc TEGRA_SWGROUP_VDE>; 64*4882a593Smuzhiyun}; 65