1*4882a593Smuzhiyun* Mediatek Video Processor Unit 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunVideo Processor Unit is a HW video controller. It controls HW Codec including 4*4882a593SmuzhiyunH.264/VP8/VP9 Decode, H.264/VP8 Encode and Image Processor (scale/rotate/color convert). 5*4882a593Smuzhiyun 6*4882a593SmuzhiyunRequired properties: 7*4882a593Smuzhiyun - compatible: "mediatek,mt8173-vpu" 8*4882a593Smuzhiyun - reg: Must contain an entry for each entry in reg-names. 9*4882a593Smuzhiyun - reg-names: Must include the following entries: 10*4882a593Smuzhiyun "tcm": tcm base 11*4882a593Smuzhiyun "cfg_reg": Main configuration registers base 12*4882a593Smuzhiyun - interrupts: interrupt number to the cpu. 13*4882a593Smuzhiyun - clocks : clock name from clock manager 14*4882a593Smuzhiyun - clock-names: must be main. It is the main clock of VPU 15*4882a593Smuzhiyun 16*4882a593SmuzhiyunOptional properties: 17*4882a593Smuzhiyun - memory-region: phandle to a node describing memory (see 18*4882a593Smuzhiyun Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt) 19*4882a593Smuzhiyun to be used for VPU extended memory; if not present, VPU may be located 20*4882a593Smuzhiyun anywhere in the memory 21*4882a593Smuzhiyun 22*4882a593SmuzhiyunExample: 23*4882a593Smuzhiyun vpu: vpu@10020000 { 24*4882a593Smuzhiyun compatible = "mediatek,mt8173-vpu"; 25*4882a593Smuzhiyun reg = <0 0x10020000 0 0x30000>, 26*4882a593Smuzhiyun <0 0x10050000 0 0x100>; 27*4882a593Smuzhiyun reg-names = "tcm", "cfg_reg"; 28*4882a593Smuzhiyun interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; 29*4882a593Smuzhiyun clocks = <&topckgen TOP_SCP_SEL>; 30*4882a593Smuzhiyun clock-names = "main"; 31*4882a593Smuzhiyun }; 32