1*4882a593Smuzhiyun* Mediatek Media Data Path 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunMedia Data Path is used for scaling and color space conversion. 4*4882a593Smuzhiyun 5*4882a593SmuzhiyunRequired properties (controller node): 6*4882a593Smuzhiyun- compatible: "mediatek,mt8173-mdp" 7*4882a593Smuzhiyun- mediatek,vpu: the node of video processor unit, see 8*4882a593Smuzhiyun Documentation/devicetree/bindings/media/mediatek-vpu.txt for details. 9*4882a593Smuzhiyun 10*4882a593SmuzhiyunRequired properties (all function blocks, child node): 11*4882a593Smuzhiyun- compatible: Should be one of 12*4882a593Smuzhiyun "mediatek,mt8173-mdp-rdma" - read DMA 13*4882a593Smuzhiyun "mediatek,mt8173-mdp-rsz" - resizer 14*4882a593Smuzhiyun "mediatek,mt8173-mdp-wdma" - write DMA 15*4882a593Smuzhiyun "mediatek,mt8173-mdp-wrot" - write DMA with rotation 16*4882a593Smuzhiyun- reg: Physical base address and length of the function block register space 17*4882a593Smuzhiyun- clocks: device clocks, see 18*4882a593Smuzhiyun Documentation/devicetree/bindings/clock/clock-bindings.txt for details. 19*4882a593Smuzhiyun- power-domains: a phandle to the power domain, see 20*4882a593Smuzhiyun Documentation/devicetree/bindings/power/power_domain.txt for details. 21*4882a593Smuzhiyun 22*4882a593SmuzhiyunRequired properties (DMA function blocks, child node): 23*4882a593Smuzhiyun- compatible: Should be one of 24*4882a593Smuzhiyun "mediatek,mt8173-mdp-rdma" 25*4882a593Smuzhiyun "mediatek,mt8173-mdp-wdma" 26*4882a593Smuzhiyun "mediatek,mt8173-mdp-wrot" 27*4882a593Smuzhiyun- iommus: should point to the respective IOMMU block with master port as 28*4882a593Smuzhiyun argument, see Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml 29*4882a593Smuzhiyun for details. 30*4882a593Smuzhiyun- mediatek,larb: must contain the local arbiters in the current Socs, see 31*4882a593Smuzhiyun Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.txt 32*4882a593Smuzhiyun for details. 33*4882a593Smuzhiyun 34*4882a593SmuzhiyunExample: 35*4882a593Smuzhiyun mdp_rdma0: rdma@14001000 { 36*4882a593Smuzhiyun compatible = "mediatek,mt8173-mdp-rdma"; 37*4882a593Smuzhiyun "mediatek,mt8173-mdp"; 38*4882a593Smuzhiyun reg = <0 0x14001000 0 0x1000>; 39*4882a593Smuzhiyun clocks = <&mmsys CLK_MM_MDP_RDMA0>, 40*4882a593Smuzhiyun <&mmsys CLK_MM_MUTEX_32K>; 41*4882a593Smuzhiyun power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 42*4882a593Smuzhiyun iommus = <&iommu M4U_PORT_MDP_RDMA0>; 43*4882a593Smuzhiyun mediatek,larb = <&larb0>; 44*4882a593Smuzhiyun mediatek,vpu = <&vpu>; 45*4882a593Smuzhiyun }; 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun mdp_rdma1: rdma@14002000 { 48*4882a593Smuzhiyun compatible = "mediatek,mt8173-mdp-rdma"; 49*4882a593Smuzhiyun reg = <0 0x14002000 0 0x1000>; 50*4882a593Smuzhiyun clocks = <&mmsys CLK_MM_MDP_RDMA1>, 51*4882a593Smuzhiyun <&mmsys CLK_MM_MUTEX_32K>; 52*4882a593Smuzhiyun power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 53*4882a593Smuzhiyun iommus = <&iommu M4U_PORT_MDP_RDMA1>; 54*4882a593Smuzhiyun mediatek,larb = <&larb4>; 55*4882a593Smuzhiyun }; 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun mdp_rsz0: rsz@14003000 { 58*4882a593Smuzhiyun compatible = "mediatek,mt8173-mdp-rsz"; 59*4882a593Smuzhiyun reg = <0 0x14003000 0 0x1000>; 60*4882a593Smuzhiyun clocks = <&mmsys CLK_MM_MDP_RSZ0>; 61*4882a593Smuzhiyun power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 62*4882a593Smuzhiyun }; 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun mdp_rsz1: rsz@14004000 { 65*4882a593Smuzhiyun compatible = "mediatek,mt8173-mdp-rsz"; 66*4882a593Smuzhiyun reg = <0 0x14004000 0 0x1000>; 67*4882a593Smuzhiyun clocks = <&mmsys CLK_MM_MDP_RSZ1>; 68*4882a593Smuzhiyun power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 69*4882a593Smuzhiyun }; 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun mdp_rsz2: rsz@14005000 { 72*4882a593Smuzhiyun compatible = "mediatek,mt8173-mdp-rsz"; 73*4882a593Smuzhiyun reg = <0 0x14005000 0 0x1000>; 74*4882a593Smuzhiyun clocks = <&mmsys CLK_MM_MDP_RSZ2>; 75*4882a593Smuzhiyun power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 76*4882a593Smuzhiyun }; 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun mdp_wdma0: wdma@14006000 { 79*4882a593Smuzhiyun compatible = "mediatek,mt8173-mdp-wdma"; 80*4882a593Smuzhiyun reg = <0 0x14006000 0 0x1000>; 81*4882a593Smuzhiyun clocks = <&mmsys CLK_MM_MDP_WDMA>; 82*4882a593Smuzhiyun power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 83*4882a593Smuzhiyun iommus = <&iommu M4U_PORT_MDP_WDMA>; 84*4882a593Smuzhiyun mediatek,larb = <&larb0>; 85*4882a593Smuzhiyun }; 86*4882a593Smuzhiyun 87*4882a593Smuzhiyun mdp_wrot0: wrot@14007000 { 88*4882a593Smuzhiyun compatible = "mediatek,mt8173-mdp-wrot"; 89*4882a593Smuzhiyun reg = <0 0x14007000 0 0x1000>; 90*4882a593Smuzhiyun clocks = <&mmsys CLK_MM_MDP_WROT0>; 91*4882a593Smuzhiyun power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 92*4882a593Smuzhiyun iommus = <&iommu M4U_PORT_MDP_WROT0>; 93*4882a593Smuzhiyun mediatek,larb = <&larb0>; 94*4882a593Smuzhiyun }; 95*4882a593Smuzhiyun 96*4882a593Smuzhiyun mdp_wrot1: wrot@14008000 { 97*4882a593Smuzhiyun compatible = "mediatek,mt8173-mdp-wrot"; 98*4882a593Smuzhiyun reg = <0 0x14008000 0 0x1000>; 99*4882a593Smuzhiyun clocks = <&mmsys CLK_MM_MDP_WROT1>; 100*4882a593Smuzhiyun power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; 101*4882a593Smuzhiyun iommus = <&iommu M4U_PORT_MDP_WROT1>; 102*4882a593Smuzhiyun mediatek,larb = <&larb4>; 103*4882a593Smuzhiyun }; 104