xref: /OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/media/mediatek-jpeg-encoder.txt (revision 4882a59341e53eb6f0b4789bf948001014eff981) 
1*4882a593Smuzhiyun* MediaTek JPEG Encoder
2*4882a593Smuzhiyun
3*4882a593SmuzhiyunMediaTek JPEG Encoder is the JPEG encode hardware present in MediaTek SoCs
4*4882a593Smuzhiyun
5*4882a593SmuzhiyunRequired properties:
6*4882a593Smuzhiyun- compatible : "mediatek,mt2701-jpgenc"
7*4882a593Smuzhiyun  followed by "mediatek,mtk-jpgenc"
8*4882a593Smuzhiyun- reg : physical base address of the JPEG encoder registers and length of
9*4882a593Smuzhiyun  memory mapped region.
10*4882a593Smuzhiyun- interrupts : interrupt number to the interrupt controller.
11*4882a593Smuzhiyun- clocks: device clocks, see
12*4882a593Smuzhiyun  Documentation/devicetree/bindings/clock/clock-bindings.txt for details.
13*4882a593Smuzhiyun- clock-names: must contain "jpgenc". It is the clock of JPEG encoder.
14*4882a593Smuzhiyun- power-domains: a phandle to the power domain, see
15*4882a593Smuzhiyun  Documentation/devicetree/bindings/power/power_domain.txt for details.
16*4882a593Smuzhiyun- mediatek,larb: must contain the local arbiters in the current SoCs, see
17*4882a593Smuzhiyun  Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.txt
18*4882a593Smuzhiyun  for details.
19*4882a593Smuzhiyun- iommus: should point to the respective IOMMU block with master port as
20*4882a593Smuzhiyun  argument, see Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml
21*4882a593Smuzhiyun  for details.
22*4882a593Smuzhiyun
23*4882a593SmuzhiyunExample:
24*4882a593Smuzhiyun	jpegenc: jpegenc@1500a000 {
25*4882a593Smuzhiyun		compatible = "mediatek,mt2701-jpgenc",
26*4882a593Smuzhiyun			     "mediatek,mtk-jpgenc";
27*4882a593Smuzhiyun		reg = <0 0x1500a000 0 0x1000>;
28*4882a593Smuzhiyun		interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_LOW>;
29*4882a593Smuzhiyun		clocks =  <&imgsys CLK_IMG_VENC>;
30*4882a593Smuzhiyun		clock-names = "jpgenc";
31*4882a593Smuzhiyun		power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>;
32*4882a593Smuzhiyun		mediatek,larb = <&larb2>;
33*4882a593Smuzhiyun		iommus = <&iommu MT2701_M4U_PORT_JPGENC_RDMA>,
34*4882a593Smuzhiyun			 <&iommu MT2701_M4U_PORT_JPGENC_BSDMA>;
35*4882a593Smuzhiyun	};
36