1*4882a593Smuzhiyun* Mediatek JPEG Decoder 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunMediatek JPEG Decoder is the JPEG decode hardware present in Mediatek SoCs 4*4882a593Smuzhiyun 5*4882a593SmuzhiyunRequired properties: 6*4882a593Smuzhiyun- compatible : must be one of the following string: 7*4882a593Smuzhiyun "mediatek,mt8173-jpgdec" 8*4882a593Smuzhiyun "mediatek,mt7623-jpgdec", "mediatek,mt2701-jpgdec" 9*4882a593Smuzhiyun "mediatek,mt2701-jpgdec" 10*4882a593Smuzhiyun- reg : physical base address of the jpeg decoder registers and length of 11*4882a593Smuzhiyun memory mapped region. 12*4882a593Smuzhiyun- interrupts : interrupt number to the interrupt controller. 13*4882a593Smuzhiyun- clocks: device clocks, see 14*4882a593Smuzhiyun Documentation/devicetree/bindings/clock/clock-bindings.txt for details. 15*4882a593Smuzhiyun- clock-names: must contain "jpgdec-smi" and "jpgdec". 16*4882a593Smuzhiyun- power-domains: a phandle to the power domain, see 17*4882a593Smuzhiyun Documentation/devicetree/bindings/power/power_domain.txt for details. 18*4882a593Smuzhiyun- mediatek,larb: must contain the local arbiters in the current Socs, see 19*4882a593Smuzhiyun Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.txt 20*4882a593Smuzhiyun for details. 21*4882a593Smuzhiyun- iommus: should point to the respective IOMMU block with master port as 22*4882a593Smuzhiyun argument, see Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml 23*4882a593Smuzhiyun for details. 24*4882a593Smuzhiyun 25*4882a593SmuzhiyunExample: 26*4882a593Smuzhiyun jpegdec: jpegdec@15004000 { 27*4882a593Smuzhiyun compatible = "mediatek,mt2701-jpgdec"; 28*4882a593Smuzhiyun reg = <0 0x15004000 0 0x1000>; 29*4882a593Smuzhiyun interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_LOW>; 30*4882a593Smuzhiyun clocks = <&imgsys CLK_IMG_JPGDEC_SMI>, 31*4882a593Smuzhiyun <&imgsys CLK_IMG_JPGDEC>; 32*4882a593Smuzhiyun clock-names = "jpgdec-smi", 33*4882a593Smuzhiyun "jpgdec"; 34*4882a593Smuzhiyun power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>; 35*4882a593Smuzhiyun mediatek,larb = <&larb2>; 36*4882a593Smuzhiyun iommus = <&iommu MT2701_M4U_PORT_JPGDEC_WDMA>, 37*4882a593Smuzhiyun <&iommu MT2701_M4U_PORT_JPGDEC_BSDMA>; 38*4882a593Smuzhiyun }; 39