xref: /OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/media/imx7-mipi-csi2.txt (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593SmuzhiyunFreescale i.MX7 Mipi CSI2
2*4882a593Smuzhiyun=========================
3*4882a593Smuzhiyun
4*4882a593Smuzhiyunmipi_csi2 node
5*4882a593Smuzhiyun--------------
6*4882a593Smuzhiyun
7*4882a593SmuzhiyunThis is the device node for the MIPI CSI-2 receiver core in i.MX7 SoC. It is
8*4882a593Smuzhiyuncompatible with previous version of Samsung D-phy.
9*4882a593Smuzhiyun
10*4882a593SmuzhiyunRequired properties:
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun- compatible    : "fsl,imx7-mipi-csi2";
13*4882a593Smuzhiyun- reg           : base address and length of the register set for the device;
14*4882a593Smuzhiyun- interrupts    : should contain MIPI CSIS interrupt;
15*4882a593Smuzhiyun- clocks        : list of clock specifiers, see
16*4882a593Smuzhiyun        Documentation/devicetree/bindings/clock/clock-bindings.txt for details;
17*4882a593Smuzhiyun- clock-names   : must contain "pclk", "wrap" and "phy" entries, matching
18*4882a593Smuzhiyun                  entries in the clock property;
19*4882a593Smuzhiyun- power-domains : a phandle to the power domain, see
20*4882a593Smuzhiyun          Documentation/devicetree/bindings/power/power_domain.txt for details.
21*4882a593Smuzhiyun- reset-names   : should include following entry "mrst";
22*4882a593Smuzhiyun- resets        : a list of phandle, should contain reset entry of
23*4882a593Smuzhiyun                  reset-names;
24*4882a593Smuzhiyun- phy-supply    : from the generic phy bindings, a phandle to a regulator that
25*4882a593Smuzhiyun	          provides power to MIPI CSIS core;
26*4882a593Smuzhiyun
27*4882a593SmuzhiyunOptional properties:
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun- clock-frequency : The IP's main (system bus) clock frequency in Hz, default
30*4882a593Smuzhiyun		    value when this property is not specified is 166 MHz;
31*4882a593Smuzhiyun- fsl,csis-hs-settle : differential receiver (HS-RX) settle time;
32*4882a593Smuzhiyun
33*4882a593SmuzhiyunThe device node should contain two 'port' child nodes with one child 'endpoint'
34*4882a593Smuzhiyunnode, according to the bindings defined in:
35*4882a593Smuzhiyun Documentation/devicetree/bindings/ media/video-interfaces.txt.
36*4882a593Smuzhiyun The following are properties specific to those nodes.
37*4882a593Smuzhiyun
38*4882a593Smuzhiyunport node
39*4882a593Smuzhiyun---------
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun- reg		  : (required) can take the values 0 or 1, where 0 shall be
42*4882a593Smuzhiyun                     related to the sink port and port 1 shall be the source
43*4882a593Smuzhiyun                     one;
44*4882a593Smuzhiyun
45*4882a593Smuzhiyunendpoint node
46*4882a593Smuzhiyun-------------
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun- data-lanes    : (required) an array specifying active physical MIPI-CSI2
49*4882a593Smuzhiyun		    data input lanes and their mapping to logical lanes; this
50*4882a593Smuzhiyun                    shall only be applied to port 0 (sink port), the array's
51*4882a593Smuzhiyun                    content is unused only its length is meaningful,
52*4882a593Smuzhiyun                    in this case the maximum length supported is 2;
53*4882a593Smuzhiyun
54*4882a593Smuzhiyunexample:
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun        mipi_csi: mipi-csi@30750000 {
57*4882a593Smuzhiyun                #address-cells = <1>;
58*4882a593Smuzhiyun                #size-cells = <0>;
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun                compatible = "fsl,imx7-mipi-csi2";
61*4882a593Smuzhiyun                reg = <0x30750000 0x10000>;
62*4882a593Smuzhiyun                interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
63*4882a593Smuzhiyun                clocks = <&clks IMX7D_IPG_ROOT_CLK>,
64*4882a593Smuzhiyun                                <&clks IMX7D_MIPI_CSI_ROOT_CLK>,
65*4882a593Smuzhiyun                                <&clks IMX7D_MIPI_DPHY_ROOT_CLK>;
66*4882a593Smuzhiyun                clock-names = "pclk", "wrap", "phy";
67*4882a593Smuzhiyun                clock-frequency = <166000000>;
68*4882a593Smuzhiyun                power-domains = <&pgc_mipi_phy>;
69*4882a593Smuzhiyun                phy-supply = <&reg_1p0d>;
70*4882a593Smuzhiyun                resets = <&src IMX7_RESET_MIPI_PHY_MRST>;
71*4882a593Smuzhiyun                reset-names = "mrst";
72*4882a593Smuzhiyun                fsl,csis-hs-settle = <3>;
73*4882a593Smuzhiyun
74*4882a593Smuzhiyun                port@0 {
75*4882a593Smuzhiyun                        reg = <0>;
76*4882a593Smuzhiyun
77*4882a593Smuzhiyun                        mipi_from_sensor: endpoint {
78*4882a593Smuzhiyun                                remote-endpoint = <&ov2680_to_mipi>;
79*4882a593Smuzhiyun                                data-lanes = <1>;
80*4882a593Smuzhiyun                        };
81*4882a593Smuzhiyun                };
82*4882a593Smuzhiyun
83*4882a593Smuzhiyun                port@1 {
84*4882a593Smuzhiyun                        reg = <1>;
85*4882a593Smuzhiyun
86*4882a593Smuzhiyun                        mipi_vc0_to_csi_mux: endpoint {
87*4882a593Smuzhiyun                                remote-endpoint = <&csi_mux_from_mipi_vc0>;
88*4882a593Smuzhiyun                        };
89*4882a593Smuzhiyun                };
90*4882a593Smuzhiyun        };
91