1*4882a593Smuzhiyun* ImgTec Infrared (IR) decoder version 1 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunThis binding is for Imagination Technologies' Infrared decoder block, 4*4882a593Smuzhiyunspecifically major revision 1. 5*4882a593Smuzhiyun 6*4882a593SmuzhiyunRequired properties: 7*4882a593Smuzhiyun- compatible: Should be "img,ir-rev1" 8*4882a593Smuzhiyun- reg: Physical base address of the controller and length of 9*4882a593Smuzhiyun memory mapped region. 10*4882a593Smuzhiyun- interrupts: The interrupt specifier to the cpu. 11*4882a593Smuzhiyun 12*4882a593SmuzhiyunOptional properties: 13*4882a593Smuzhiyun- clocks: List of clock specifiers as described in standard 14*4882a593Smuzhiyun clock bindings. 15*4882a593Smuzhiyun Up to 3 clocks may be specified in the following order: 16*4882a593Smuzhiyun 1st: Core clock (defaults to 32.768KHz if omitted). 17*4882a593Smuzhiyun 2nd: System side (fast) clock. 18*4882a593Smuzhiyun 3rd: Power modulation clock. 19*4882a593Smuzhiyun- clock-names: List of clock names corresponding to the clocks 20*4882a593Smuzhiyun specified in the clocks property. 21*4882a593Smuzhiyun Accepted clock names are: 22*4882a593Smuzhiyun "core": Core clock. 23*4882a593Smuzhiyun "sys": System clock. 24*4882a593Smuzhiyun "mod": Power modulation clock. 25*4882a593Smuzhiyun 26*4882a593SmuzhiyunExample: 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun ir@2006200 { 29*4882a593Smuzhiyun compatible = "img,ir-rev1"; 30*4882a593Smuzhiyun reg = <0x02006200 0x100>; 31*4882a593Smuzhiyun interrupts = <29 4>; 32*4882a593Smuzhiyun clocks = <&clk_32khz>; 33*4882a593Smuzhiyun clock-names = "core"; 34*4882a593Smuzhiyun }; 35