xref: /OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/media/i2c/st,st-mipid02.txt (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593SmuzhiyunSTMicroelectronics MIPID02 CSI-2 to PARALLEL bridge
2*4882a593Smuzhiyun
3*4882a593SmuzhiyunMIPID02 has two CSI-2 input ports, only one of those ports can be active at a
4*4882a593Smuzhiyuntime. Active port input stream will be de-serialized and its content outputted
5*4882a593Smuzhiyunthrough PARALLEL output port.
6*4882a593SmuzhiyunCSI-2 first input port is a dual lane 800Mbps per lane whereas CSI-2 second
7*4882a593Smuzhiyuninput port is a single lane 800Mbps. Both ports support clock and data lane
8*4882a593Smuzhiyunpolarity swap. First port also supports data lane swap.
9*4882a593SmuzhiyunPARALLEL output port has a maximum width of 12 bits.
10*4882a593SmuzhiyunSupported formats are RAW6, RAW7, RAW8, RAW10, RAW12, RGB565, RGB888, RGB444,
11*4882a593SmuzhiyunYUV420 8-bit, YUV422 8-bit and YUV420 10-bit.
12*4882a593Smuzhiyun
13*4882a593SmuzhiyunRequired Properties:
14*4882a593Smuzhiyun- compatible: shall be "st,st-mipid02"
15*4882a593Smuzhiyun- clocks: reference to the xclk input clock.
16*4882a593Smuzhiyun- clock-names: shall be "xclk".
17*4882a593Smuzhiyun- VDDE-supply: sensor digital IO supply. Must be 1.8 volts.
18*4882a593Smuzhiyun- VDDIN-supply: sensor internal regulator supply. Must be 1.8 volts.
19*4882a593Smuzhiyun
20*4882a593SmuzhiyunOptional Properties:
21*4882a593Smuzhiyun- reset-gpios: reference to the GPIO connected to the xsdn pin, if any.
22*4882a593Smuzhiyun	       This is an active low signal to the mipid02.
23*4882a593Smuzhiyun
24*4882a593SmuzhiyunRequired subnodes:
25*4882a593Smuzhiyun  - ports: A ports node with one port child node per device input and output
26*4882a593Smuzhiyun	   port, in accordance with the video interface bindings defined in
27*4882a593Smuzhiyun	   Documentation/devicetree/bindings/media/video-interfaces.txt. The
28*4882a593Smuzhiyun	   port nodes are numbered as follows:
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun	   Port Description
31*4882a593Smuzhiyun	   -----------------------------
32*4882a593Smuzhiyun	   0    CSI-2 first input port
33*4882a593Smuzhiyun	   1    CSI-2 second input port
34*4882a593Smuzhiyun	   2    PARALLEL output
35*4882a593Smuzhiyun
36*4882a593SmuzhiyunEndpoint node required property for CSI-2 connection is:
37*4882a593Smuzhiyun- data-lanes: shall be <1> for Port 1. for Port 0 dual-lane operation shall be
38*4882a593Smuzhiyun<1 2> or <2 1>. For Port 0 single-lane operation shall be <1> or <2>.
39*4882a593SmuzhiyunEndpoint node optional property for CSI-2 connection is:
40*4882a593Smuzhiyun- lane-polarities: any lane can be inverted or not.
41*4882a593Smuzhiyun
42*4882a593SmuzhiyunEndpoint node required property for PARALLEL connection is:
43*4882a593Smuzhiyun- bus-width: shall be set to <6>, <7>, <8>, <10> or <12>.
44*4882a593SmuzhiyunEndpoint node optional properties for PARALLEL connection are:
45*4882a593Smuzhiyun- hsync-active: active state of the HSYNC signal, 0/1 for LOW/HIGH respectively.
46*4882a593SmuzhiyunLOW being the default.
47*4882a593Smuzhiyun- vsync-active: active state of the VSYNC signal, 0/1 for LOW/HIGH respectively.
48*4882a593SmuzhiyunLOW being the default.
49*4882a593Smuzhiyun
50*4882a593SmuzhiyunExample:
51*4882a593Smuzhiyun
52*4882a593Smuzhiyunmipid02: csi2rx@14 {
53*4882a593Smuzhiyun	compatible = "st,st-mipid02";
54*4882a593Smuzhiyun	reg = <0x14>;
55*4882a593Smuzhiyun	status = "okay";
56*4882a593Smuzhiyun	clocks = <&clk_ext_camera_12>;
57*4882a593Smuzhiyun	clock-names = "xclk";
58*4882a593Smuzhiyun	VDDE-supply = <&vdd>;
59*4882a593Smuzhiyun	VDDIN-supply = <&vdd>;
60*4882a593Smuzhiyun	ports {
61*4882a593Smuzhiyun		#address-cells = <1>;
62*4882a593Smuzhiyun		#size-cells = <0>;
63*4882a593Smuzhiyun		port@0 {
64*4882a593Smuzhiyun			reg = <0>;
65*4882a593Smuzhiyun
66*4882a593Smuzhiyun			ep0: endpoint {
67*4882a593Smuzhiyun				data-lanes = <1 2>;
68*4882a593Smuzhiyun				remote-endpoint = <&mipi_csi2_in>;
69*4882a593Smuzhiyun			};
70*4882a593Smuzhiyun		};
71*4882a593Smuzhiyun		port@2 {
72*4882a593Smuzhiyun			reg = <2>;
73*4882a593Smuzhiyun
74*4882a593Smuzhiyun			ep2: endpoint {
75*4882a593Smuzhiyun				bus-width = <8>;
76*4882a593Smuzhiyun				hsync-active = <0>;
77*4882a593Smuzhiyun				vsync-active = <0>;
78*4882a593Smuzhiyun				remote-endpoint = <&parallel_out>;
79*4882a593Smuzhiyun			};
80*4882a593Smuzhiyun		};
81*4882a593Smuzhiyun	};
82*4882a593Smuzhiyun};
83