xref: /OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/media/i2c/chrontel,ch7322.yaml (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2*4882a593Smuzhiyun%YAML 1.2
3*4882a593Smuzhiyun---
4*4882a593Smuzhiyun$id: "http://devicetree.org/schemas/media/i2c/chrontel,ch7322.yaml#"
5*4882a593Smuzhiyun$schema: "http://devicetree.org/meta-schemas/core.yaml#"
6*4882a593Smuzhiyun
7*4882a593Smuzhiyuntitle: Chrontel HDMI-CEC Controller
8*4882a593Smuzhiyun
9*4882a593Smuzhiyunmaintainers:
10*4882a593Smuzhiyun  - Jeff Chase <jnchase@google.com>
11*4882a593Smuzhiyun
12*4882a593Smuzhiyundescription:
13*4882a593Smuzhiyun  The Chrontel CH7322 is a discrete HDMI-CEC controller. It is
14*4882a593Smuzhiyun  programmable through I2C and drives a single CEC line.
15*4882a593Smuzhiyun
16*4882a593Smuzhiyunproperties:
17*4882a593Smuzhiyun  compatible:
18*4882a593Smuzhiyun    const: chrontel,ch7322
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun  reg:
21*4882a593Smuzhiyun    description: I2C device address
22*4882a593Smuzhiyun    maxItems: 1
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun  clocks:
25*4882a593Smuzhiyun    maxItems: 1
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun  interrupts:
28*4882a593Smuzhiyun    maxItems: 1
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun  reset-gpios:
31*4882a593Smuzhiyun    description:
32*4882a593Smuzhiyun      Reference to the GPIO connected to the RESET pin, if any. This
33*4882a593Smuzhiyun      pin is active-low.
34*4882a593Smuzhiyun    maxItems: 1
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun  standby-gpios:
37*4882a593Smuzhiyun    description:
38*4882a593Smuzhiyun      Reference to the GPIO connected to the OE pin, if any. When low
39*4882a593Smuzhiyun      the device will respond to power status requests with "standby"
40*4882a593Smuzhiyun      if in auto mode.
41*4882a593Smuzhiyun    maxItems: 1
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun  # see ../cec.txt
44*4882a593Smuzhiyun  hdmi-phandle:
45*4882a593Smuzhiyun    description: phandle to the HDMI controller
46*4882a593Smuzhiyun
47*4882a593Smuzhiyunrequired:
48*4882a593Smuzhiyun  - compatible
49*4882a593Smuzhiyun  - reg
50*4882a593Smuzhiyun  - interrupts
51*4882a593Smuzhiyun
52*4882a593SmuzhiyunadditionalProperties: false
53*4882a593Smuzhiyun
54*4882a593Smuzhiyunexamples:
55*4882a593Smuzhiyun  - |
56*4882a593Smuzhiyun    #include <dt-bindings/gpio/gpio.h>
57*4882a593Smuzhiyun    #include <dt-bindings/interrupt-controller/irq.h>
58*4882a593Smuzhiyun    i2c {
59*4882a593Smuzhiyun      #address-cells = <1>;
60*4882a593Smuzhiyun      #size-cells = <0>;
61*4882a593Smuzhiyun      ch7322@75 {
62*4882a593Smuzhiyun        compatible = "chrontel,ch7322";
63*4882a593Smuzhiyun        reg = <0x75>;
64*4882a593Smuzhiyun        interrupts = <47 IRQ_TYPE_EDGE_RISING>;
65*4882a593Smuzhiyun        standby-gpios = <&gpio 16 GPIO_ACTIVE_LOW>;
66*4882a593Smuzhiyun        reset-gpios = <&gpio 15 GPIO_ACTIVE_LOW>;
67*4882a593Smuzhiyun        hdmi-phandle = <&hdmi>;
68*4882a593Smuzhiyun      };
69*4882a593Smuzhiyun    };
70