1*4882a593SmuzhiyunFreescale Pixel Pipeline 2*4882a593Smuzhiyun======================== 3*4882a593Smuzhiyun 4*4882a593SmuzhiyunThe Pixel Pipeline (PXP) is a memory-to-memory graphics processing engine 5*4882a593Smuzhiyunthat supports scaling, colorspace conversion, alpha blending, rotation, and 6*4882a593Smuzhiyunpixel conversion via lookup table. Different versions are present on various 7*4882a593Smuzhiyuni.MX SoCs from i.MX23 to i.MX7. 8*4882a593Smuzhiyun 9*4882a593SmuzhiyunRequired properties: 10*4882a593Smuzhiyun- compatible: should be "fsl,<soc>-pxp", where SoC can be one of imx23, imx28, 11*4882a593Smuzhiyun imx6dl, imx6sl, imx6sll, imx6ul, imx6sx, imx6ull, or imx7d. 12*4882a593Smuzhiyun- reg: the register base and size for the device registers 13*4882a593Smuzhiyun- interrupts: the PXP interrupt, two interrupts for imx6ull and imx7d. 14*4882a593Smuzhiyun- clock-names: should be "axi" 15*4882a593Smuzhiyun- clocks: the PXP AXI clock 16*4882a593Smuzhiyun 17*4882a593SmuzhiyunExample: 18*4882a593Smuzhiyun 19*4882a593Smuzhiyunpxp@21cc000 { 20*4882a593Smuzhiyun compatible = "fsl,imx6ull-pxp"; 21*4882a593Smuzhiyun reg = <0x021cc000 0x4000>; 22*4882a593Smuzhiyun interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 23*4882a593Smuzhiyun <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 24*4882a593Smuzhiyun clock-names = "axi"; 25*4882a593Smuzhiyun clocks = <&clks IMX6UL_CLK_PXP>; 26*4882a593Smuzhiyun}; 27