1*4882a593SmuzhiyunChips&Media Coda multi-standard codec IP 2*4882a593Smuzhiyun======================================== 3*4882a593Smuzhiyun 4*4882a593SmuzhiyunCoda codec IPs are present in i.MX SoCs in various versions, 5*4882a593Smuzhiyuncalled VPU (Video Processing Unit). 6*4882a593Smuzhiyun 7*4882a593SmuzhiyunRequired properties: 8*4882a593Smuzhiyun- compatible : should be "fsl,<chip>-src" for i.MX SoCs: 9*4882a593Smuzhiyun (a) "fsl,imx27-vpu" for CodaDx6 present in i.MX27 10*4882a593Smuzhiyun (b) "fsl,imx51-vpu" for CodaHx4 present in i.MX51 11*4882a593Smuzhiyun (c) "fsl,imx53-vpu" for CODA7541 present in i.MX53 12*4882a593Smuzhiyun (d) "fsl,imx6q-vpu" for CODA960 present in i.MX6q 13*4882a593Smuzhiyun- reg: should be register base and length as documented in the 14*4882a593Smuzhiyun SoC reference manual 15*4882a593Smuzhiyun- interrupts : Should contain the VPU interrupt. For CODA960, 16*4882a593Smuzhiyun a second interrupt is needed for the MJPEG unit. 17*4882a593Smuzhiyun- clocks : Should contain the ahb and per clocks, in the order 18*4882a593Smuzhiyun determined by the clock-names property. 19*4882a593Smuzhiyun- clock-names : Should be "ahb", "per" 20*4882a593Smuzhiyun- iram : phandle pointing to the SRAM device node 21*4882a593Smuzhiyun 22*4882a593SmuzhiyunExample: 23*4882a593Smuzhiyun 24*4882a593Smuzhiyunvpu: vpu@63ff4000 { 25*4882a593Smuzhiyun compatible = "fsl,imx53-vpu"; 26*4882a593Smuzhiyun reg = <0x63ff4000 0x1000>; 27*4882a593Smuzhiyun interrupts = <9>; 28*4882a593Smuzhiyun clocks = <&clks 63>, <&clks 63>; 29*4882a593Smuzhiyun clock-names = "ahb", "per"; 30*4882a593Smuzhiyun iram = <&ocram>; 31*4882a593Smuzhiyun}; 32