1*4882a593Smuzhiyun# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 2*4882a593Smuzhiyun%YAML 1.2 3*4882a593Smuzhiyun--- 4*4882a593Smuzhiyun$id: http://devicetree.org/schemas/media/allwinner,sun8i-h3-deinterlace.yaml# 5*4882a593Smuzhiyun$schema: http://devicetree.org/meta-schemas/core.yaml# 6*4882a593Smuzhiyun 7*4882a593Smuzhiyuntitle: Allwinner H3 Deinterlace Device Tree Bindings 8*4882a593Smuzhiyun 9*4882a593Smuzhiyunmaintainers: 10*4882a593Smuzhiyun - Jernej Skrabec <jernej.skrabec@siol.net> 11*4882a593Smuzhiyun - Chen-Yu Tsai <wens@csie.org> 12*4882a593Smuzhiyun - Maxime Ripard <mripard@kernel.org> 13*4882a593Smuzhiyun 14*4882a593Smuzhiyundescription: |- 15*4882a593Smuzhiyun The Allwinner H3 and later has a deinterlace core used for 16*4882a593Smuzhiyun deinterlacing interlaced video content. 17*4882a593Smuzhiyun 18*4882a593Smuzhiyunproperties: 19*4882a593Smuzhiyun compatible: 20*4882a593Smuzhiyun oneOf: 21*4882a593Smuzhiyun - const: allwinner,sun8i-h3-deinterlace 22*4882a593Smuzhiyun - items: 23*4882a593Smuzhiyun - const: allwinner,sun50i-a64-deinterlace 24*4882a593Smuzhiyun - const: allwinner,sun8i-h3-deinterlace 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun reg: 27*4882a593Smuzhiyun maxItems: 1 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun interrupts: 30*4882a593Smuzhiyun maxItems: 1 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun clocks: 33*4882a593Smuzhiyun items: 34*4882a593Smuzhiyun - description: Deinterlace interface clock 35*4882a593Smuzhiyun - description: Deinterlace module clock 36*4882a593Smuzhiyun - description: Deinterlace DRAM clock 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun clock-names: 39*4882a593Smuzhiyun items: 40*4882a593Smuzhiyun - const: bus 41*4882a593Smuzhiyun - const: mod 42*4882a593Smuzhiyun - const: ram 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun resets: 45*4882a593Smuzhiyun maxItems: 1 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun interconnects: 48*4882a593Smuzhiyun maxItems: 1 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun interconnect-names: 51*4882a593Smuzhiyun const: dma-mem 52*4882a593Smuzhiyun 53*4882a593Smuzhiyunrequired: 54*4882a593Smuzhiyun - compatible 55*4882a593Smuzhiyun - reg 56*4882a593Smuzhiyun - interrupts 57*4882a593Smuzhiyun - clocks 58*4882a593Smuzhiyun 59*4882a593SmuzhiyunadditionalProperties: false 60*4882a593Smuzhiyun 61*4882a593Smuzhiyunexamples: 62*4882a593Smuzhiyun - | 63*4882a593Smuzhiyun #include <dt-bindings/interrupt-controller/arm-gic.h> 64*4882a593Smuzhiyun #include <dt-bindings/clock/sun8i-h3-ccu.h> 65*4882a593Smuzhiyun #include <dt-bindings/reset/sun8i-h3-ccu.h> 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun deinterlace: deinterlace@1400000 { 68*4882a593Smuzhiyun compatible = "allwinner,sun8i-h3-deinterlace"; 69*4882a593Smuzhiyun reg = <0x01400000 0x20000>; 70*4882a593Smuzhiyun clocks = <&ccu CLK_BUS_DEINTERLACE>, 71*4882a593Smuzhiyun <&ccu CLK_DEINTERLACE>, 72*4882a593Smuzhiyun <&ccu CLK_DRAM_DEINTERLACE>; 73*4882a593Smuzhiyun clock-names = "bus", "mod", "ram"; 74*4882a593Smuzhiyun resets = <&ccu RST_BUS_DEINTERLACE>; 75*4882a593Smuzhiyun interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 76*4882a593Smuzhiyun interconnects = <&mbus 9>; 77*4882a593Smuzhiyun interconnect-names = "dma-mem"; 78*4882a593Smuzhiyun }; 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun... 81