1*4882a593Smuzhiyun# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 2*4882a593Smuzhiyun%YAML 1.2 3*4882a593Smuzhiyun--- 4*4882a593Smuzhiyun$id: "http://devicetree.org/schemas/mailbox/st,stm32-ipcc.yaml#" 5*4882a593Smuzhiyun$schema: "http://devicetree.org/meta-schemas/core.yaml#" 6*4882a593Smuzhiyun 7*4882a593Smuzhiyuntitle: STMicroelectronics STM32 IPC controller bindings 8*4882a593Smuzhiyun 9*4882a593Smuzhiyundescription: 10*4882a593Smuzhiyun The IPCC block provides a non blocking signaling mechanism to post and 11*4882a593Smuzhiyun retrieve messages in an atomic way between two processors. 12*4882a593Smuzhiyun It provides the signaling for N bidirectionnal channels. The number of 13*4882a593Smuzhiyun channels (N) can be read from a dedicated register. 14*4882a593Smuzhiyun 15*4882a593Smuzhiyunmaintainers: 16*4882a593Smuzhiyun - Fabien Dessenne <fabien.dessenne@st.com> 17*4882a593Smuzhiyun - Arnaud Pouliquen <arnaud.pouliquen@st.com> 18*4882a593Smuzhiyun 19*4882a593Smuzhiyunproperties: 20*4882a593Smuzhiyun compatible: 21*4882a593Smuzhiyun const: st,stm32mp1-ipcc 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun reg: 24*4882a593Smuzhiyun maxItems: 1 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun clocks: 27*4882a593Smuzhiyun maxItems: 1 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun interrupts: 30*4882a593Smuzhiyun items: 31*4882a593Smuzhiyun - description: rx channel occupied 32*4882a593Smuzhiyun - description: tx channel free 33*4882a593Smuzhiyun - description: wakeup source 34*4882a593Smuzhiyun minItems: 2 35*4882a593Smuzhiyun maxItems: 3 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun interrupt-names: 38*4882a593Smuzhiyun items: 39*4882a593Smuzhiyun - const: rx 40*4882a593Smuzhiyun - const: tx 41*4882a593Smuzhiyun - const: wakeup 42*4882a593Smuzhiyun minItems: 2 43*4882a593Smuzhiyun maxItems: 3 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun wakeup-source: true 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun "#mbox-cells": 48*4882a593Smuzhiyun const: 1 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun st,proc-id: 51*4882a593Smuzhiyun description: Processor id using the mailbox (0 or 1) 52*4882a593Smuzhiyun $ref: /schemas/types.yaml#/definitions/uint32 53*4882a593Smuzhiyun enum: [0, 1] 54*4882a593Smuzhiyun 55*4882a593Smuzhiyunrequired: 56*4882a593Smuzhiyun - compatible 57*4882a593Smuzhiyun - reg 58*4882a593Smuzhiyun - st,proc-id 59*4882a593Smuzhiyun - clocks 60*4882a593Smuzhiyun - interrupt-names 61*4882a593Smuzhiyun - "#mbox-cells" 62*4882a593Smuzhiyun - interrupts 63*4882a593Smuzhiyun 64*4882a593SmuzhiyunadditionalProperties: false 65*4882a593Smuzhiyun 66*4882a593Smuzhiyunexamples: 67*4882a593Smuzhiyun - | 68*4882a593Smuzhiyun #include <dt-bindings/interrupt-controller/arm-gic.h> 69*4882a593Smuzhiyun #include <dt-bindings/clock/stm32mp1-clks.h> 70*4882a593Smuzhiyun ipcc: mailbox@4c001000 { 71*4882a593Smuzhiyun compatible = "st,stm32mp1-ipcc"; 72*4882a593Smuzhiyun #mbox-cells = <1>; 73*4882a593Smuzhiyun reg = <0x4c001000 0x400>; 74*4882a593Smuzhiyun st,proc-id = <0>; 75*4882a593Smuzhiyun interrupts-extended = <&intc GIC_SPI 100 IRQ_TYPE_NONE>, 76*4882a593Smuzhiyun <&intc GIC_SPI 101 IRQ_TYPE_NONE>, 77*4882a593Smuzhiyun <&aiec 62 1>; 78*4882a593Smuzhiyun interrupt-names = "rx", "tx", "wakeup"; 79*4882a593Smuzhiyun clocks = <&rcc_clk IPCC>; 80*4882a593Smuzhiyun wakeup-source; 81*4882a593Smuzhiyun }; 82*4882a593Smuzhiyun 83*4882a593Smuzhiyun... 84