1*4882a593SmuzhiyunRockchip mailbox 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunThe Rockchip mailbox is used by the Rockchip CPU cores to communicate 4*4882a593Smuzhiyunrequests to MCU processor. 5*4882a593Smuzhiyun 6*4882a593SmuzhiyunRefer to ./mailbox.txt for generic information about mailbox device-tree 7*4882a593Smuzhiyunbindings. 8*4882a593Smuzhiyun 9*4882a593SmuzhiyunRequired properties: 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun - compatible: should be one of the following. 12*4882a593Smuzhiyun - "rockchip,rk3368-mbox" for rk3368 13*4882a593Smuzhiyun - reg: physical base address of the controller and length of memory mapped 14*4882a593Smuzhiyun region. 15*4882a593Smuzhiyun - interrupts: The interrupt number to the cpu. The interrupt specifier format 16*4882a593Smuzhiyun depends on the interrupt controller. 17*4882a593Smuzhiyun - #mbox-cells: Common mailbox binding property to identify the number 18*4882a593Smuzhiyun of cells required for the mailbox specifier. Should be 1 19*4882a593Smuzhiyun 20*4882a593SmuzhiyunOptional properties : 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun - wakeup-source: Mailbox irq can be used as a wakeup source. 23*4882a593Smuzhiyun - rockchip,txpoll-period-ms: TX Done polling interval in milliseconds. 24*4882a593Smuzhiyun 25*4882a593SmuzhiyunExample: 26*4882a593Smuzhiyun-------- 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun/* RK3368 */ 29*4882a593Smuzhiyunmbox: mbox@ff6b0000 { 30*4882a593Smuzhiyun compatible = "rockchip,rk3368-mailbox"; 31*4882a593Smuzhiyun reg = <0x0 0xff6b0000 0x0 0x1000>, 32*4882a593Smuzhiyun interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 33*4882a593Smuzhiyun <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 34*4882a593Smuzhiyun <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 35*4882a593Smuzhiyun <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>; 36*4882a593Smuzhiyun #mbox-cells = <1>; 37*4882a593Smuzhiyun}; 38