1*4882a593Smuzhiyun# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause 2*4882a593Smuzhiyun%YAML 1.2 3*4882a593Smuzhiyun--- 4*4882a593Smuzhiyun$id: http://devicetree.org/schemas/mailbox/qcom-ipcc.yaml# 5*4882a593Smuzhiyun$schema: http://devicetree.org/meta-schemas/core.yaml# 6*4882a593Smuzhiyun 7*4882a593Smuzhiyuntitle: Qualcomm Technologies, Inc. Inter-Processor Communication Controller 8*4882a593Smuzhiyun 9*4882a593Smuzhiyunmaintainers: 10*4882a593Smuzhiyun - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> 11*4882a593Smuzhiyun 12*4882a593Smuzhiyundescription: 13*4882a593Smuzhiyun The Inter-Processor Communication Controller (IPCC) is a centralized hardware 14*4882a593Smuzhiyun to route interrupts across various subsystems. It involves a three-level 15*4882a593Smuzhiyun addressing scheme called protocol, client and signal. For example, consider an 16*4882a593Smuzhiyun entity on the Application Processor Subsystem (APSS) that wants to listen to 17*4882a593Smuzhiyun Modem's interrupts via Shared Memory Point to Point (SMP2P) interface. In such 18*4882a593Smuzhiyun a case, the client would be Modem (client-id is 2) and the signal would be 19*4882a593Smuzhiyun SMP2P (signal-id is 2). The SMP2P itself falls under the Multiprocessor (MPROC) 20*4882a593Smuzhiyun protocol (protocol-id is 0). Refer include/dt-bindings/mailbox/qcom-ipcc.h 21*4882a593Smuzhiyun for the list of such IDs. 22*4882a593Smuzhiyun 23*4882a593Smuzhiyunproperties: 24*4882a593Smuzhiyun compatible: 25*4882a593Smuzhiyun items: 26*4882a593Smuzhiyun - enum: 27*4882a593Smuzhiyun - qcom,sm8250-ipcc 28*4882a593Smuzhiyun - const: qcom,ipcc 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun reg: 31*4882a593Smuzhiyun maxItems: 1 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun interrupts: 34*4882a593Smuzhiyun maxItems: 1 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun interrupt-controller: true 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun "#interrupt-cells": 39*4882a593Smuzhiyun const: 3 40*4882a593Smuzhiyun description: 41*4882a593Smuzhiyun The first cell is the client-id, the second cell is the signal-id and the 42*4882a593Smuzhiyun third cell is the interrupt type. 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun "#mbox-cells": 45*4882a593Smuzhiyun const: 2 46*4882a593Smuzhiyun description: 47*4882a593Smuzhiyun The first cell is the client-id, and the second cell is the signal-id. 48*4882a593Smuzhiyun 49*4882a593Smuzhiyunrequired: 50*4882a593Smuzhiyun - compatible 51*4882a593Smuzhiyun - reg 52*4882a593Smuzhiyun - interrupts 53*4882a593Smuzhiyun - interrupt-controller 54*4882a593Smuzhiyun - "#interrupt-cells" 55*4882a593Smuzhiyun - "#mbox-cells" 56*4882a593Smuzhiyun 57*4882a593SmuzhiyunadditionalProperties: false 58*4882a593Smuzhiyun 59*4882a593Smuzhiyunexamples: 60*4882a593Smuzhiyun - | 61*4882a593Smuzhiyun #include <dt-bindings/interrupt-controller/arm-gic.h> 62*4882a593Smuzhiyun #include <dt-bindings/mailbox/qcom-ipcc.h> 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun mailbox@408000 { 65*4882a593Smuzhiyun compatible = "qcom,sm8250-ipcc", "qcom,ipcc"; 66*4882a593Smuzhiyun reg = <0x408000 0x1000>; 67*4882a593Smuzhiyun interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 68*4882a593Smuzhiyun interrupt-controller; 69*4882a593Smuzhiyun #interrupt-cells = <3>; 70*4882a593Smuzhiyun #mbox-cells = <2>; 71*4882a593Smuzhiyun }; 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun smp2p-modem { 74*4882a593Smuzhiyun compatible = "qcom,smp2p"; 75*4882a593Smuzhiyun interrupts-extended = <&ipcc_mproc IPCC_CLIENT_MPSS 76*4882a593Smuzhiyun IPCC_MPROC_SIGNAL_SMP2P IRQ_TYPE_EDGE_RISING>; 77*4882a593Smuzhiyun mboxes = <&ipcc_mproc IPCC_CLIENT_MPSS IPCC_MPROC_SIGNAL_SMP2P>; 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun /* Other SMP2P fields */ 80*4882a593Smuzhiyun }; 81