1*4882a593SmuzhiyunNVIDIA Tegra Hardware Synchronization Primitives (HSP) 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunThe HSP modules are used for the processors to share resources and communicate 4*4882a593Smuzhiyuntogether. It provides a set of hardware synchronization primitives for 5*4882a593Smuzhiyuninterprocessor communication. So the interprocessor communication (IPC) 6*4882a593Smuzhiyunprotocols can use hardware synchronization primitives, when operating between 7*4882a593Smuzhiyuntwo processors not in an SMP relationship. 8*4882a593Smuzhiyun 9*4882a593SmuzhiyunThe features that HSP supported are shared mailboxes, shared semaphores, 10*4882a593Smuzhiyunarbitrated semaphores and doorbells. 11*4882a593Smuzhiyun 12*4882a593SmuzhiyunRequired properties: 13*4882a593Smuzhiyun- name : Should be hsp 14*4882a593Smuzhiyun- compatible 15*4882a593Smuzhiyun Array of strings. 16*4882a593Smuzhiyun one of: 17*4882a593Smuzhiyun - "nvidia,tegra186-hsp" 18*4882a593Smuzhiyun - "nvidia,tegra194-hsp", "nvidia,tegra186-hsp" 19*4882a593Smuzhiyun- reg : Offset and length of the register set for the device. 20*4882a593Smuzhiyun- interrupt-names 21*4882a593Smuzhiyun Array of strings. 22*4882a593Smuzhiyun Contains a list of names for the interrupts described by the interrupt 23*4882a593Smuzhiyun property. May contain the following entries, in any order: 24*4882a593Smuzhiyun - "doorbell" 25*4882a593Smuzhiyun - "sharedN", where 'N' is a number from zero up to the number of 26*4882a593Smuzhiyun external interrupts supported by the HSP instance minus one. 27*4882a593Smuzhiyun Users of this binding MUST look up entries in the interrupt property 28*4882a593Smuzhiyun by name, using this interrupt-names property to do so. 29*4882a593Smuzhiyun- interrupts 30*4882a593Smuzhiyun Array of interrupt specifiers. 31*4882a593Smuzhiyun Must contain one entry per entry in the interrupt-names property, 32*4882a593Smuzhiyun in a matching order. 33*4882a593Smuzhiyun- #mbox-cells : Should be 2. 34*4882a593Smuzhiyun 35*4882a593SmuzhiyunThe mbox specifier of the "mboxes" property in the client node should contain 36*4882a593Smuzhiyuntwo cells. The first cell determines the HSP type and the second cell is used 37*4882a593Smuzhiyunto identify the mailbox that the client is going to use. 38*4882a593Smuzhiyun 39*4882a593SmuzhiyunFor doorbells, the second cell specifies the index of the doorbell to use. 40*4882a593Smuzhiyun 41*4882a593SmuzhiyunFor shared mailboxes, the second cell is composed of two fields: 42*4882a593Smuzhiyun- bits 31..24: 43*4882a593Smuzhiyun A bit mask of flags that further specify how the shared mailbox will be 44*4882a593Smuzhiyun used. Valid flags are: 45*4882a593Smuzhiyun - bit 31: 46*4882a593Smuzhiyun Defines the direction of the mailbox. If set, the mailbox will be used 47*4882a593Smuzhiyun as a producer (i.e. used to send data). If cleared, the mailbox is the 48*4882a593Smuzhiyun consumer of data sent by a producer. 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun- bits 23.. 0: 51*4882a593Smuzhiyun The index of the shared mailbox to use. The number of available mailboxes 52*4882a593Smuzhiyun may vary by instance of the HSP block and SoC generation. 53*4882a593Smuzhiyun 54*4882a593SmuzhiyunThe following file contains definitions that can be used to construct mailbox 55*4882a593Smuzhiyunspecifiers: 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun <dt-bindings/mailbox/tegra186-hsp.h> 58*4882a593Smuzhiyun 59*4882a593SmuzhiyunExample: 60*4882a593Smuzhiyun 61*4882a593Smuzhiyunhsp_top0: hsp@3c00000 { 62*4882a593Smuzhiyun compatible = "nvidia,tegra186-hsp"; 63*4882a593Smuzhiyun reg = <0x0 0x03c00000 0x0 0xa0000>; 64*4882a593Smuzhiyun interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; 65*4882a593Smuzhiyun interrupt-names = "doorbell"; 66*4882a593Smuzhiyun #mbox-cells = <2>; 67*4882a593Smuzhiyun}; 68*4882a593Smuzhiyun 69*4882a593Smuzhiyunclient { 70*4882a593Smuzhiyun ... 71*4882a593Smuzhiyun mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB TEGRA_HSP_DB_MASTER_XXX>; 72*4882a593Smuzhiyun}; 73