1*4882a593SmuzhiyunMediaTek GCE 2*4882a593Smuzhiyun=============== 3*4882a593Smuzhiyun 4*4882a593SmuzhiyunThe Global Command Engine (GCE) is used to help read/write registers with 5*4882a593Smuzhiyuncritical time limitation, such as updating display configuration during the 6*4882a593Smuzhiyunvblank. The GCE can be used to implement the Command Queue (CMDQ) driver. 7*4882a593Smuzhiyun 8*4882a593SmuzhiyunCMDQ driver uses mailbox framework for communication. Please refer to 9*4882a593Smuzhiyunmailbox.txt for generic information about mailbox device-tree bindings. 10*4882a593Smuzhiyun 11*4882a593SmuzhiyunRequired properties: 12*4882a593Smuzhiyun- compatible: can be "mediatek,mt8173-gce", "mediatek,mt8183-gce" or 13*4882a593Smuzhiyun "mediatek,mt6779-gce". 14*4882a593Smuzhiyun- reg: Address range of the GCE unit 15*4882a593Smuzhiyun- interrupts: The interrupt signal from the GCE block 16*4882a593Smuzhiyun- clock: Clocks according to the common clock binding 17*4882a593Smuzhiyun- clock-names: Must be "gce" to stand for GCE clock 18*4882a593Smuzhiyun- #mbox-cells: Should be 2. 19*4882a593Smuzhiyun <&phandle channel priority> 20*4882a593Smuzhiyun phandle: Label name of a gce node. 21*4882a593Smuzhiyun channel: Channel of mailbox. Be equal to the thread id of GCE. 22*4882a593Smuzhiyun priority: Priority of GCE thread. 23*4882a593Smuzhiyun 24*4882a593SmuzhiyunRequired properties for a client device: 25*4882a593Smuzhiyun- mboxes: Client use mailbox to communicate with GCE, it should have this 26*4882a593Smuzhiyun property and list of phandle, mailbox specifiers. 27*4882a593SmuzhiyunOptional properties for a client device: 28*4882a593Smuzhiyun- mediatek,gce-client-reg: Specify the sub-system id which is corresponding 29*4882a593Smuzhiyun to the register address, it should have this property and list of phandle, 30*4882a593Smuzhiyun sub-system specifiers. 31*4882a593Smuzhiyun <&phandle subsys_number start_offset size> 32*4882a593Smuzhiyun phandle: Label name of a gce node. 33*4882a593Smuzhiyun subsys_number: specify the sub-system id which is corresponding 34*4882a593Smuzhiyun to the register address. 35*4882a593Smuzhiyun start_offset: the start offset of register address that GCE can access. 36*4882a593Smuzhiyun size: the total size of register address that GCE can access. 37*4882a593Smuzhiyun 38*4882a593SmuzhiyunSome vaules of properties are defined in 'dt-bindings/gce/mt8173-gce.h', 39*4882a593Smuzhiyun'dt-binding/gce/mt8183-gce.h' or 'dt-bindings/gce/mt6779-gce.h'. Such as 40*4882a593Smuzhiyunsub-system ids, thread priority, event ids. 41*4882a593Smuzhiyun 42*4882a593SmuzhiyunExample: 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun gce: gce@10212000 { 45*4882a593Smuzhiyun compatible = "mediatek,mt8173-gce"; 46*4882a593Smuzhiyun reg = <0 0x10212000 0 0x1000>; 47*4882a593Smuzhiyun interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_LOW>; 48*4882a593Smuzhiyun clocks = <&infracfg CLK_INFRA_GCE>; 49*4882a593Smuzhiyun clock-names = "gce"; 50*4882a593Smuzhiyun #mbox-cells = <2>; 51*4882a593Smuzhiyun }; 52*4882a593Smuzhiyun 53*4882a593SmuzhiyunExample for a client device: 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun mmsys: clock-controller@14000000 { 56*4882a593Smuzhiyun compatible = "mediatek,mt8173-mmsys"; 57*4882a593Smuzhiyun mboxes = <&gce 0 CMDQ_THR_PRIO_LOWEST>, 58*4882a593Smuzhiyun <&gce 1 CMDQ_THR_PRIO_LOWEST>; 59*4882a593Smuzhiyun mutex-event-eof = <CMDQ_EVENT_MUTEX0_STREAM_EOF 60*4882a593Smuzhiyun CMDQ_EVENT_MUTEX1_STREAM_EOF>; 61*4882a593Smuzhiyun mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x3000 0x1000>, 62*4882a593Smuzhiyun <&gce SUBSYS_1401XXXX 0x2000 0x100>; 63*4882a593Smuzhiyun ... 64*4882a593Smuzhiyun }; 65