1*4882a593SmuzhiyunThe PDC driver manages data transfer to and from various offload engines 2*4882a593Smuzhiyunon some Broadcom SoCs. An SoC may have multiple PDC hardware blocks. There is 3*4882a593Smuzhiyunone device tree entry per block. On some chips, the PDC functionality is 4*4882a593Smuzhiyunhandled by the FA2 (Northstar Plus). 5*4882a593Smuzhiyun 6*4882a593SmuzhiyunRequired properties: 7*4882a593Smuzhiyun- compatible : Should be "brcm,iproc-pdc-mbox" or "brcm,iproc-fa2-mbox" for 8*4882a593Smuzhiyun FA2/Northstar Plus. 9*4882a593Smuzhiyun- reg: Should contain PDC registers location and length. 10*4882a593Smuzhiyun- interrupts: Should contain the IRQ line for the PDC. 11*4882a593Smuzhiyun- #mbox-cells: 1 12*4882a593Smuzhiyun- brcm,rx-status-len: Length of metadata preceding received frames, in bytes. 13*4882a593Smuzhiyun 14*4882a593SmuzhiyunOptional properties: 15*4882a593Smuzhiyun- brcm,use-bcm-hdr: present if a BCM header precedes each frame. 16*4882a593Smuzhiyun 17*4882a593SmuzhiyunExample: 18*4882a593Smuzhiyun pdc0: iproc-pdc0@612c0000 { 19*4882a593Smuzhiyun compatible = "brcm,iproc-pdc-mbox"; 20*4882a593Smuzhiyun reg = <0 0x612c0000 0 0x445>; /* PDC FS0 regs */ 21*4882a593Smuzhiyun interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; 22*4882a593Smuzhiyun #mbox-cells = <1>; /* one cell per mailbox channel */ 23*4882a593Smuzhiyun brcm,rx-status-len = <32>; 24*4882a593Smuzhiyun brcm,use-bcm-hdr; 25*4882a593Smuzhiyun }; 26