1*4882a593SmuzhiyunBroadcom FlexRM Ring Manager 2*4882a593Smuzhiyun============================ 3*4882a593SmuzhiyunThe Broadcom FlexRM ring manager provides a set of rings which can be 4*4882a593Smuzhiyunused to submit work to offload engines. An SoC may have multiple FlexRM 5*4882a593Smuzhiyunhardware blocks. There is one device tree entry per FlexRM block. The 6*4882a593SmuzhiyunFlexRM driver will create a mailbox-controller instance for given FlexRM 7*4882a593Smuzhiyunhardware block where each mailbox channel is a separate FlexRM ring. 8*4882a593Smuzhiyun 9*4882a593SmuzhiyunRequired properties: 10*4882a593Smuzhiyun-------------------- 11*4882a593Smuzhiyun- compatible: Should be "brcm,iproc-flexrm-mbox" 12*4882a593Smuzhiyun- reg: Specifies base physical address and size of the FlexRM 13*4882a593Smuzhiyun ring registers 14*4882a593Smuzhiyun- msi-parent: Phandles (and potential Device IDs) to MSI controllers 15*4882a593Smuzhiyun The FlexRM engine will send MSIs (instead of wired 16*4882a593Smuzhiyun interrupts) to CPU. There is one MSI for each FlexRM ring. 17*4882a593Smuzhiyun Refer devicetree/bindings/interrupt-controller/msi.txt 18*4882a593Smuzhiyun- #mbox-cells: Specifies the number of cells needed to encode a mailbox 19*4882a593Smuzhiyun channel. This should be 3. 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun The 1st cell is the mailbox channel number. 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun The 2nd cell contains MSI completion threshold. This is the 24*4882a593Smuzhiyun number of completion messages for which FlexRM will inject 25*4882a593Smuzhiyun one MSI interrupt to CPU. 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun The 3nd cell contains MSI timer value representing time for 28*4882a593Smuzhiyun which FlexRM will wait to accumulate N completion messages 29*4882a593Smuzhiyun where N is the value specified by 2nd cell above. If FlexRM 30*4882a593Smuzhiyun does not get required number of completion messages in time 31*4882a593Smuzhiyun specified by this cell then it will inject one MSI interrupt 32*4882a593Smuzhiyun to CPU provided atleast one completion message is available. 33*4882a593Smuzhiyun 34*4882a593SmuzhiyunOptional properties: 35*4882a593Smuzhiyun-------------------- 36*4882a593Smuzhiyun- dma-coherent: Present if DMA operations made by the FlexRM engine (such 37*4882a593Smuzhiyun as DMA descriptor access, access to buffers pointed by DMA 38*4882a593Smuzhiyun descriptors and read/write pointer updates to DDR) are 39*4882a593Smuzhiyun cache coherent with the CPU. 40*4882a593Smuzhiyun 41*4882a593SmuzhiyunExample: 42*4882a593Smuzhiyun-------- 43*4882a593Smuzhiyuncrypto_mbox: mbox@67000000 { 44*4882a593Smuzhiyun compatible = "brcm,iproc-flexrm-mbox"; 45*4882a593Smuzhiyun reg = <0x67000000 0x200000>; 46*4882a593Smuzhiyun msi-parent = <&gic_its 0x7f00>; 47*4882a593Smuzhiyun #mbox-cells = <3>; 48*4882a593Smuzhiyun}; 49*4882a593Smuzhiyun 50*4882a593Smuzhiyuncrypto@672c0000 { 51*4882a593Smuzhiyun compatible = "brcm,spu2-v2-crypto"; 52*4882a593Smuzhiyun reg = <0x672c0000 0x1000>; 53*4882a593Smuzhiyun mboxes = <&crypto_mbox 0 0x1 0xffff>, 54*4882a593Smuzhiyun <&crypto_mbox 1 0x1 0xffff>, 55*4882a593Smuzhiyun <&crypto_mbox 16 0x1 0xffff>, 56*4882a593Smuzhiyun <&crypto_mbox 17 0x1 0xffff>, 57*4882a593Smuzhiyun <&crypto_mbox 30 0x1 0xffff>, 58*4882a593Smuzhiyun <&crypto_mbox 31 0x1 0xffff>; 59*4882a593Smuzhiyun}; 60