1*4882a593Smuzhiyun# SPDX-License-Identifier: GPL-2.0 2*4882a593Smuzhiyun%YAML 1.2 3*4882a593Smuzhiyun--- 4*4882a593Smuzhiyun$id: http://devicetree.org/schemas/mailbox/allwinner,sun6i-a31-msgbox.yaml# 5*4882a593Smuzhiyun$schema: http://devicetree.org/meta-schemas/core.yaml# 6*4882a593Smuzhiyun 7*4882a593Smuzhiyuntitle: Allwinner sunxi Message Box 8*4882a593Smuzhiyun 9*4882a593Smuzhiyunmaintainers: 10*4882a593Smuzhiyun - Samuel Holland <samuel@sholland.org> 11*4882a593Smuzhiyun 12*4882a593Smuzhiyundescription: | 13*4882a593Smuzhiyun The hardware message box on sun6i, sun8i, sun9i, and sun50i SoCs is a 14*4882a593Smuzhiyun two-user mailbox controller containing 8 unidirectional FIFOs. An interrupt 15*4882a593Smuzhiyun is raised for received messages, but software must poll to know when a 16*4882a593Smuzhiyun transmitted message has been acknowledged by the remote user. Each FIFO can 17*4882a593Smuzhiyun hold four 32-bit messages; when a FIFO is full, clients must wait before 18*4882a593Smuzhiyun attempting more transmissions. 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun Refer to ./mailbox.txt for generic information about mailbox device-tree 21*4882a593Smuzhiyun bindings. 22*4882a593Smuzhiyun 23*4882a593Smuzhiyunproperties: 24*4882a593Smuzhiyun compatible: 25*4882a593Smuzhiyun oneOf: 26*4882a593Smuzhiyun - items: 27*4882a593Smuzhiyun - enum: 28*4882a593Smuzhiyun - allwinner,sun8i-a83t-msgbox 29*4882a593Smuzhiyun - allwinner,sun8i-h3-msgbox 30*4882a593Smuzhiyun - allwinner,sun9i-a80-msgbox 31*4882a593Smuzhiyun - allwinner,sun50i-a64-msgbox 32*4882a593Smuzhiyun - allwinner,sun50i-h6-msgbox 33*4882a593Smuzhiyun - const: allwinner,sun6i-a31-msgbox 34*4882a593Smuzhiyun - const: allwinner,sun6i-a31-msgbox 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun reg: 37*4882a593Smuzhiyun maxItems: 1 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun clocks: 40*4882a593Smuzhiyun maxItems: 1 41*4882a593Smuzhiyun description: bus clock 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun resets: 44*4882a593Smuzhiyun maxItems: 1 45*4882a593Smuzhiyun description: bus reset 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun interrupts: 48*4882a593Smuzhiyun maxItems: 1 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun '#mbox-cells': 51*4882a593Smuzhiyun const: 1 52*4882a593Smuzhiyun description: first cell is the channel number (0-7) 53*4882a593Smuzhiyun 54*4882a593Smuzhiyunrequired: 55*4882a593Smuzhiyun - compatible 56*4882a593Smuzhiyun - reg 57*4882a593Smuzhiyun - clocks 58*4882a593Smuzhiyun - resets 59*4882a593Smuzhiyun - interrupts 60*4882a593Smuzhiyun - '#mbox-cells' 61*4882a593Smuzhiyun 62*4882a593SmuzhiyunadditionalProperties: false 63*4882a593Smuzhiyun 64*4882a593Smuzhiyunexamples: 65*4882a593Smuzhiyun - | 66*4882a593Smuzhiyun #include <dt-bindings/clock/sun8i-h3-ccu.h> 67*4882a593Smuzhiyun #include <dt-bindings/interrupt-controller/arm-gic.h> 68*4882a593Smuzhiyun #include <dt-bindings/reset/sun8i-h3-ccu.h> 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun msgbox: mailbox@1c17000 { 71*4882a593Smuzhiyun compatible = "allwinner,sun8i-h3-msgbox", 72*4882a593Smuzhiyun "allwinner,sun6i-a31-msgbox"; 73*4882a593Smuzhiyun reg = <0x01c17000 0x1000>; 74*4882a593Smuzhiyun clocks = <&ccu CLK_BUS_MSGBOX>; 75*4882a593Smuzhiyun resets = <&ccu RST_BUS_MSGBOX>; 76*4882a593Smuzhiyun interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 77*4882a593Smuzhiyun #mbox-cells = <1>; 78*4882a593Smuzhiyun }; 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun... 81