1*4882a593SmuzhiyunOMAP2+ IOMMU 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunRequired properties: 4*4882a593Smuzhiyun- compatible : Should be one of, 5*4882a593Smuzhiyun "ti,omap2-iommu" for OMAP2/OMAP3 IOMMU instances 6*4882a593Smuzhiyun "ti,omap4-iommu" for OMAP4/OMAP5 IOMMU instances 7*4882a593Smuzhiyun "ti,dra7-dsp-iommu" for DRA7xx DSP IOMMU instances 8*4882a593Smuzhiyun "ti,dra7-iommu" for DRA7xx IOMMU instances 9*4882a593Smuzhiyun- ti,hwmods : Name of the hwmod associated with the IOMMU instance 10*4882a593Smuzhiyun- reg : Address space for the configuration registers 11*4882a593Smuzhiyun- interrupts : Interrupt specifier for the IOMMU instance 12*4882a593Smuzhiyun- #iommu-cells : Should be 0. OMAP IOMMUs are all "single-master" devices, 13*4882a593Smuzhiyun and needs no additional data in the pargs specifier. Please 14*4882a593Smuzhiyun also refer to the generic bindings document for more info 15*4882a593Smuzhiyun on this property, 16*4882a593Smuzhiyun Documentation/devicetree/bindings/iommu/iommu.txt 17*4882a593Smuzhiyun 18*4882a593SmuzhiyunOptional properties: 19*4882a593Smuzhiyun- ti,#tlb-entries : Number of entries in the translation look-aside buffer. 20*4882a593Smuzhiyun Should be either 8 or 32 (default: 32) 21*4882a593Smuzhiyun- ti,iommu-bus-err-back : Indicates the IOMMU instance supports throwing 22*4882a593Smuzhiyun back a bus error response on MMU faults. 23*4882a593Smuzhiyun- ti,syscon-mmuconfig : Should be a pair of the phandle to the DSP_SYSTEM 24*4882a593Smuzhiyun syscon node that contains the additional control 25*4882a593Smuzhiyun register for enabling the MMU, and the MMU instance 26*4882a593Smuzhiyun number (0-indexed) within the sub-system. This property 27*4882a593Smuzhiyun is required for DSP IOMMU instances on DRA7xx SoCs. The 28*4882a593Smuzhiyun instance number should be 0 for DSP MDMA MMUs and 1 for 29*4882a593Smuzhiyun DSP EDMA MMUs. 30*4882a593Smuzhiyun 31*4882a593SmuzhiyunExample: 32*4882a593Smuzhiyun /* OMAP3 ISP MMU */ 33*4882a593Smuzhiyun mmu_isp: mmu@480bd400 { 34*4882a593Smuzhiyun #iommu-cells = <0>; 35*4882a593Smuzhiyun compatible = "ti,omap2-iommu"; 36*4882a593Smuzhiyun reg = <0x480bd400 0x80>; 37*4882a593Smuzhiyun interrupts = <24>; 38*4882a593Smuzhiyun ti,hwmods = "mmu_isp"; 39*4882a593Smuzhiyun ti,#tlb-entries = <8>; 40*4882a593Smuzhiyun }; 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun /* DRA74x DSP2 MMUs */ 43*4882a593Smuzhiyun mmu0_dsp2: mmu@41501000 { 44*4882a593Smuzhiyun compatible = "ti,dra7-dsp-iommu"; 45*4882a593Smuzhiyun reg = <0x41501000 0x100>; 46*4882a593Smuzhiyun interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 47*4882a593Smuzhiyun ti,hwmods = "mmu0_dsp2"; 48*4882a593Smuzhiyun #iommu-cells = <0>; 49*4882a593Smuzhiyun ti,syscon-mmuconfig = <&dsp2_system 0x0>; 50*4882a593Smuzhiyun }; 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun mmu1_dsp2: mmu@41502000 { 53*4882a593Smuzhiyun compatible = "ti,dra7-dsp-iommu"; 54*4882a593Smuzhiyun reg = <0x41502000 0x100>; 55*4882a593Smuzhiyun interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; 56*4882a593Smuzhiyun ti,hwmods = "mmu1_dsp2"; 57*4882a593Smuzhiyun #iommu-cells = <0>; 58*4882a593Smuzhiyun ti,syscon-mmuconfig = <&dsp2_system 0x1>; 59*4882a593Smuzhiyun }; 60