1*4882a593Smuzhiyun# SPDX-License-Identifier: GPL-2.0 2*4882a593Smuzhiyun%YAML 1.2 3*4882a593Smuzhiyun--- 4*4882a593Smuzhiyun$id: http://devicetree.org/schemas/iommu/samsung,sysmmu.yaml# 5*4882a593Smuzhiyun$schema: http://devicetree.org/meta-schemas/core.yaml# 6*4882a593Smuzhiyun 7*4882a593Smuzhiyuntitle: Samsung Exynos IOMMU H/W, System MMU (System Memory Management Unit) 8*4882a593Smuzhiyun 9*4882a593Smuzhiyunmaintainers: 10*4882a593Smuzhiyun - Marek Szyprowski <m.szyprowski@samsung.com> 11*4882a593Smuzhiyun 12*4882a593Smuzhiyundescription: |+ 13*4882a593Smuzhiyun Samsung's Exynos architecture contains System MMUs that enables scattered 14*4882a593Smuzhiyun physical memory chunks visible as a contiguous region to DMA-capable peripheral 15*4882a593Smuzhiyun devices like MFC, FIMC, FIMD, GScaler, FIMC-IS and so forth. 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun System MMU is an IOMMU and supports identical translation table format to 18*4882a593Smuzhiyun ARMv7 translation tables with minimum set of page properties including access 19*4882a593Smuzhiyun permissions, shareability and security protection. In addition, System MMU has 20*4882a593Smuzhiyun another capabilities like L2 TLB or block-fetch buffers to minimize translation 21*4882a593Smuzhiyun latency. 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun System MMUs are in many to one relation with peripheral devices, i.e. single 24*4882a593Smuzhiyun peripheral device might have multiple System MMUs (usually one for each bus 25*4882a593Smuzhiyun master), but one System MMU can handle transactions from only one peripheral 26*4882a593Smuzhiyun device. The relation between a System MMU and the peripheral device needs to be 27*4882a593Smuzhiyun defined in device node of the peripheral device. 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun MFC in all Exynos SoCs and FIMD, M2M Scalers and G2D in Exynos5420 has 2 System 30*4882a593Smuzhiyun MMUs. 31*4882a593Smuzhiyun * MFC has one System MMU on its left and right bus. 32*4882a593Smuzhiyun * FIMD in Exynos5420 has one System MMU for window 0 and 4, the other system MMU 33*4882a593Smuzhiyun for window 1, 2 and 3. 34*4882a593Smuzhiyun * M2M Scalers and G2D in Exynos5420 has one System MMU on the read channel and 35*4882a593Smuzhiyun the other System MMU on the write channel. 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun For information on assigning System MMU controller to its peripheral devices, 38*4882a593Smuzhiyun see generic IOMMU bindings. 39*4882a593Smuzhiyun 40*4882a593Smuzhiyunproperties: 41*4882a593Smuzhiyun compatible: 42*4882a593Smuzhiyun const: samsung,exynos-sysmmu 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun reg: 45*4882a593Smuzhiyun maxItems: 1 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun interrupts: 48*4882a593Smuzhiyun maxItems: 1 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun clocks: 51*4882a593Smuzhiyun minItems: 1 52*4882a593Smuzhiyun maxItems: 2 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun clock-names: 55*4882a593Smuzhiyun oneOf: 56*4882a593Smuzhiyun - items: 57*4882a593Smuzhiyun - const: sysmmu 58*4882a593Smuzhiyun - items: 59*4882a593Smuzhiyun - const: sysmmu 60*4882a593Smuzhiyun - const: master 61*4882a593Smuzhiyun - items: 62*4882a593Smuzhiyun - const: aclk 63*4882a593Smuzhiyun - const: pclk 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun "#iommu-cells": 66*4882a593Smuzhiyun const: 0 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun power-domains: 69*4882a593Smuzhiyun description: | 70*4882a593Smuzhiyun Required if the System MMU is needed to gate its power. 71*4882a593Smuzhiyun Please refer to the following document: 72*4882a593Smuzhiyun Documentation/devicetree/bindings/power/pd-samsung.yaml 73*4882a593Smuzhiyun maxItems: 1 74*4882a593Smuzhiyun 75*4882a593Smuzhiyunrequired: 76*4882a593Smuzhiyun - compatible 77*4882a593Smuzhiyun - reg 78*4882a593Smuzhiyun - interrupts 79*4882a593Smuzhiyun - clocks 80*4882a593Smuzhiyun - clock-names 81*4882a593Smuzhiyun - "#iommu-cells" 82*4882a593Smuzhiyun 83*4882a593SmuzhiyunadditionalProperties: false 84*4882a593Smuzhiyun 85*4882a593Smuzhiyunexamples: 86*4882a593Smuzhiyun - | 87*4882a593Smuzhiyun #include <dt-bindings/clock/exynos5250.h> 88*4882a593Smuzhiyun 89*4882a593Smuzhiyun gsc_0: scaler@13e00000 { 90*4882a593Smuzhiyun compatible = "samsung,exynos5-gsc"; 91*4882a593Smuzhiyun reg = <0x13e00000 0x1000>; 92*4882a593Smuzhiyun interrupts = <0 85 0>; 93*4882a593Smuzhiyun power-domains = <&pd_gsc>; 94*4882a593Smuzhiyun clocks = <&clock CLK_GSCL0>; 95*4882a593Smuzhiyun clock-names = "gscl"; 96*4882a593Smuzhiyun iommus = <&sysmmu_gsc0>; 97*4882a593Smuzhiyun }; 98*4882a593Smuzhiyun 99*4882a593Smuzhiyun sysmmu_gsc0: iommu@13e80000 { 100*4882a593Smuzhiyun compatible = "samsung,exynos-sysmmu"; 101*4882a593Smuzhiyun reg = <0x13E80000 0x1000>; 102*4882a593Smuzhiyun interrupt-parent = <&combiner>; 103*4882a593Smuzhiyun interrupts = <2 0>; 104*4882a593Smuzhiyun clock-names = "sysmmu", "master"; 105*4882a593Smuzhiyun clocks = <&clock CLK_SMMU_GSCL0>, 106*4882a593Smuzhiyun <&clock CLK_GSCL0>; 107*4882a593Smuzhiyun power-domains = <&pd_gsc>; 108*4882a593Smuzhiyun #iommu-cells = <0>; 109*4882a593Smuzhiyun }; 110*4882a593Smuzhiyun 111