1*4882a593SmuzhiyunRockchip IOMMU 2*4882a593Smuzhiyun============== 3*4882a593Smuzhiyun 4*4882a593SmuzhiyunA Rockchip DRM iommu translates io virtual addresses to physical addresses for 5*4882a593Smuzhiyunits master device. Each slave device is bound to a single master device, and 6*4882a593Smuzhiyunshares its clocks, power domain and irq. 7*4882a593Smuzhiyun 8*4882a593SmuzhiyunRequired properties: 9*4882a593Smuzhiyun- compatible : Should be "rockchip,iommu" 10*4882a593Smuzhiyun- reg : Address space for the configuration registers 11*4882a593Smuzhiyun- interrupts : Interrupt specifier for the IOMMU instance 12*4882a593Smuzhiyun- interrupt-names : Interrupt name for the IOMMU instance 13*4882a593Smuzhiyun- #iommu-cells : Should be <0>. This indicates the iommu is a 14*4882a593Smuzhiyun "single-master" device, and needs no additional information 15*4882a593Smuzhiyun to associate with its master device. See: 16*4882a593Smuzhiyun Documentation/devicetree/bindings/iommu/iommu.txt 17*4882a593Smuzhiyun- clocks : A list of clocks required for the IOMMU to be accessible by 18*4882a593Smuzhiyun the host CPU. 19*4882a593Smuzhiyun- clock-names : Should contain the following: 20*4882a593Smuzhiyun "iface" - Main peripheral bus clock (PCLK/HCL) (required) 21*4882a593Smuzhiyun "aclk" - AXI bus clock (required) 22*4882a593Smuzhiyun 23*4882a593SmuzhiyunOptional properties: 24*4882a593Smuzhiyun- rockchip,disable-mmu-reset : Don't use the mmu reset operation. 25*4882a593Smuzhiyun Some mmu instances may produce unexpected results 26*4882a593Smuzhiyun when the reset operation is used. 27*4882a593Smuzhiyun- rk_iommu,disable_reset_quirk : Same with above, for compatible with previous code 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun- rockchip,skip-mmu-read : Some iommu instances are not able to be read, skip 30*4882a593Smuzhiyun reading operation to make iommu work as normal 31*4882a593Smuzhiyun 32*4882a593SmuzhiyunExample: 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun vopl_mmu: iommu@ff940300 { 35*4882a593Smuzhiyun compatible = "rockchip,iommu"; 36*4882a593Smuzhiyun reg = <0xff940300 0x100>; 37*4882a593Smuzhiyun interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 38*4882a593Smuzhiyun interrupt-names = "vopl_mmu"; 39*4882a593Smuzhiyun clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>; 40*4882a593Smuzhiyun clock-names = "aclk", "iface"; 41*4882a593Smuzhiyun #iommu-cells = <0>; 42*4882a593Smuzhiyun }; 43