1*4882a593Smuzhiyun# SPDX-License-Identifier: GPL-2.0-only 2*4882a593Smuzhiyun%YAML 1.2 3*4882a593Smuzhiyun--- 4*4882a593Smuzhiyun$id: http://devicetree.org/schemas/iommu/arm,smmu-v3.yaml# 5*4882a593Smuzhiyun$schema: http://devicetree.org/meta-schemas/core.yaml# 6*4882a593Smuzhiyun 7*4882a593Smuzhiyuntitle: ARM SMMUv3 Architecture Implementation 8*4882a593Smuzhiyun 9*4882a593Smuzhiyunmaintainers: 10*4882a593Smuzhiyun - Will Deacon <will@kernel.org> 11*4882a593Smuzhiyun - Robin Murphy <Robin.Murphy@arm.com> 12*4882a593Smuzhiyun 13*4882a593Smuzhiyundescription: |+ 14*4882a593Smuzhiyun The SMMUv3 architecture is a significant departure from previous 15*4882a593Smuzhiyun revisions, replacing the MMIO register interface with in-memory command 16*4882a593Smuzhiyun and event queues and adding support for the ATS and PRI components of 17*4882a593Smuzhiyun the PCIe specification. 18*4882a593Smuzhiyun 19*4882a593Smuzhiyunproperties: 20*4882a593Smuzhiyun $nodename: 21*4882a593Smuzhiyun pattern: "^iommu@[0-9a-f]*" 22*4882a593Smuzhiyun compatible: 23*4882a593Smuzhiyun const: arm,smmu-v3 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun reg: 26*4882a593Smuzhiyun maxItems: 1 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun interrupts: 29*4882a593Smuzhiyun minItems: 1 30*4882a593Smuzhiyun maxItems: 4 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun interrupt-names: 33*4882a593Smuzhiyun oneOf: 34*4882a593Smuzhiyun - const: combined 35*4882a593Smuzhiyun description: 36*4882a593Smuzhiyun The combined interrupt is optional, and should only be provided if the 37*4882a593Smuzhiyun hardware supports just a single, combined interrupt line. 38*4882a593Smuzhiyun If provided, then the combined interrupt will be used in preference to 39*4882a593Smuzhiyun any others. 40*4882a593Smuzhiyun - minItems: 2 41*4882a593Smuzhiyun maxItems: 4 42*4882a593Smuzhiyun items: 43*4882a593Smuzhiyun - const: eventq # Event Queue not empty 44*4882a593Smuzhiyun - const: gerror # Global Error activated 45*4882a593Smuzhiyun - const: priq # PRI Queue not empty 46*4882a593Smuzhiyun - const: cmdq-sync # CMD_SYNC complete 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun '#iommu-cells': 49*4882a593Smuzhiyun const: 1 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun dma-coherent: 52*4882a593Smuzhiyun description: | 53*4882a593Smuzhiyun Present if page table walks made by the SMMU are cache coherent with the 54*4882a593Smuzhiyun CPU. 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun NOTE: this only applies to the SMMU itself, not masters connected 57*4882a593Smuzhiyun upstream of the SMMU. 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun msi-parent: true 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun hisilicon,broken-prefetch-cmd: 62*4882a593Smuzhiyun type: boolean 63*4882a593Smuzhiyun description: Avoid sending CMD_PREFETCH_* commands to the SMMU. 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun cavium,cn9900-broken-page1-regspace: 66*4882a593Smuzhiyun type: boolean 67*4882a593Smuzhiyun description: 68*4882a593Smuzhiyun Replaces all page 1 offsets used for EVTQ_PROD/CONS, PRIQ_PROD/CONS 69*4882a593Smuzhiyun register access with page 0 offsets. Set for Cavium ThunderX2 silicon that 70*4882a593Smuzhiyun doesn't support SMMU page1 register space. 71*4882a593Smuzhiyun 72*4882a593Smuzhiyunrequired: 73*4882a593Smuzhiyun - compatible 74*4882a593Smuzhiyun - reg 75*4882a593Smuzhiyun - '#iommu-cells' 76*4882a593Smuzhiyun 77*4882a593SmuzhiyunadditionalProperties: false 78*4882a593Smuzhiyun 79*4882a593Smuzhiyunexamples: 80*4882a593Smuzhiyun - |+ 81*4882a593Smuzhiyun #include <dt-bindings/interrupt-controller/arm-gic.h> 82*4882a593Smuzhiyun #include <dt-bindings/interrupt-controller/irq.h> 83*4882a593Smuzhiyun 84*4882a593Smuzhiyun iommu@2b400000 { 85*4882a593Smuzhiyun compatible = "arm,smmu-v3"; 86*4882a593Smuzhiyun reg = <0x2b400000 0x20000>; 87*4882a593Smuzhiyun interrupts = <GIC_SPI 74 IRQ_TYPE_EDGE_RISING>, 88*4882a593Smuzhiyun <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>, 89*4882a593Smuzhiyun <GIC_SPI 77 IRQ_TYPE_EDGE_RISING>, 90*4882a593Smuzhiyun <GIC_SPI 79 IRQ_TYPE_EDGE_RISING>; 91*4882a593Smuzhiyun interrupt-names = "eventq", "gerror", "priq", "cmdq-sync"; 92*4882a593Smuzhiyun dma-coherent; 93*4882a593Smuzhiyun #iommu-cells = <1>; 94*4882a593Smuzhiyun msi-parent = <&its 0xff0000>; 95*4882a593Smuzhiyun }; 96