1*4882a593SmuzhiyunKeystone 2 IRQ controller IP 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunOn Keystone SOCs, DSP cores can send interrupts to ARM 4*4882a593Smuzhiyunhost using the IRQ controller IP. It provides 28 IRQ signals to ARM. 5*4882a593SmuzhiyunThe IRQ handler running on HOST OS can identify DSP signal source by 6*4882a593Smuzhiyunanalyzing SRCCx bits in IPCARx registers. This is one of the component 7*4882a593Smuzhiyunused by the IPC mechanism used on Keystone SOCs. 8*4882a593Smuzhiyun 9*4882a593SmuzhiyunRequired Properties: 10*4882a593Smuzhiyun- compatible: should be "ti,keystone-irq" 11*4882a593Smuzhiyun- ti,syscon-dev : phandle and offset pair. The phandle to syscon used to 12*4882a593Smuzhiyun access device control registers and the offset inside 13*4882a593Smuzhiyun device control registers range. 14*4882a593Smuzhiyun- interrupt-controller : Identifies the node as an interrupt controller 15*4882a593Smuzhiyun- #interrupt-cells : Specifies the number of cells needed to encode interrupt 16*4882a593Smuzhiyun source should be 1. 17*4882a593Smuzhiyun- interrupts: interrupt reference to primary interrupt controller 18*4882a593Smuzhiyun 19*4882a593SmuzhiyunPlease refer to interrupts.txt in this directory for details of the common 20*4882a593SmuzhiyunInterrupt Controllers bindings used by client devices. 21*4882a593Smuzhiyun 22*4882a593SmuzhiyunExample: 23*4882a593Smuzhiyun kirq0: keystone_irq0@26202a0 { 24*4882a593Smuzhiyun compatible = "ti,keystone-irq"; 25*4882a593Smuzhiyun ti,syscon-dev = <&devctrl 0x2a0>; 26*4882a593Smuzhiyun interrupts = <GIC_SPI 4 IRQ_TYPE_EDGE_RISING>; 27*4882a593Smuzhiyun interrupt-controller; 28*4882a593Smuzhiyun #interrupt-cells = <1>; 29*4882a593Smuzhiyun }; 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun dsp0: dsp0 { 32*4882a593Smuzhiyun compatible = "linux,rproc-user"; 33*4882a593Smuzhiyun ... 34*4882a593Smuzhiyun interrupt-parent = <&kirq0>; 35*4882a593Smuzhiyun interrupts = <10 2>; 36*4882a593Smuzhiyun }; 37