1*4882a593SmuzhiyunOmap2/3 intc controller
2*4882a593Smuzhiyun
3*4882a593SmuzhiyunOn TI omap2 and 3 the intc interrupt controller can provide
4*4882a593Smuzhiyun96 or 128 IRQ signals to the ARM host depending on the SoC.
5*4882a593Smuzhiyun
6*4882a593SmuzhiyunRequired Properties:
7*4882a593Smuzhiyun- compatible: should be one of
8*4882a593Smuzhiyun			"ti,omap2-intc"
9*4882a593Smuzhiyun			"ti,omap3-intc"
10*4882a593Smuzhiyun			"ti,dm814-intc"
11*4882a593Smuzhiyun			"ti,dm816-intc"
12*4882a593Smuzhiyun			"ti,am33xx-intc"
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun- interrupt-controller : Identifies the node as an interrupt controller
15*4882a593Smuzhiyun- #interrupt-cells : Specifies the number of cells needed to encode interrupt
16*4882a593Smuzhiyun		     source, should be 1 for intc
17*4882a593Smuzhiyun- interrupts: interrupt reference to primary interrupt controller
18*4882a593Smuzhiyun
19*4882a593SmuzhiyunPlease refer to interrupts.txt in this directory for details of the common
20*4882a593SmuzhiyunInterrupt Controllers bindings used by client devices.
21*4882a593Smuzhiyun
22*4882a593SmuzhiyunExample:
23*4882a593Smuzhiyun	intc: interrupt-controller@48200000 {
24*4882a593Smuzhiyun		compatible = "ti,omap3-intc";
25*4882a593Smuzhiyun		interrupt-controller;
26*4882a593Smuzhiyun		#interrupt-cells = <1>;
27*4882a593Smuzhiyun		reg = <0x48200000 0x1000>;
28*4882a593Smuzhiyun	};
29