1*4882a593SmuzhiyunC6X Interrupt Chips
2*4882a593Smuzhiyun-------------------
3*4882a593Smuzhiyun
4*4882a593Smuzhiyun* C64X+ Core Interrupt Controller
5*4882a593Smuzhiyun
6*4882a593Smuzhiyun  The core interrupt controller provides 16 prioritized interrupts to the
7*4882a593Smuzhiyun  C64X+ core. Priority 0 and 1 are used for reset and NMI respectively.
8*4882a593Smuzhiyun  Priority 2 and 3 are reserved. Priority 4-15 are used for interrupt
9*4882a593Smuzhiyun  sources coming from outside the core.
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun  Required properties:
12*4882a593Smuzhiyun  --------------------
13*4882a593Smuzhiyun  - compatible: Should be "ti,c64x+core-pic";
14*4882a593Smuzhiyun  - #interrupt-cells: <1>
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun  Interrupt Specifier Definition
17*4882a593Smuzhiyun  ------------------------------
18*4882a593Smuzhiyun  Single cell specifying the core interrupt priority level (4-15) where
19*4882a593Smuzhiyun  4 is highest priority and 15 is lowest priority.
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun  Example
22*4882a593Smuzhiyun  -------
23*4882a593Smuzhiyun  core_pic: interrupt-controller@0 {
24*4882a593Smuzhiyun	interrupt-controller;
25*4882a593Smuzhiyun	#interrupt-cells = <1>;
26*4882a593Smuzhiyun	compatible = "ti,c64x+core-pic";
27*4882a593Smuzhiyun  };
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun* C64x+ Megamodule Interrupt Controller
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun  The megamodule PIC consists of four interrupt mupliplexers each of which
34*4882a593Smuzhiyun  combine up to 32 interrupt inputs into a single interrupt output which
35*4882a593Smuzhiyun  may be cascaded into the core interrupt controller. The megamodule PIC
36*4882a593Smuzhiyun  has a total of 12 outputs cascading into the core interrupt controller.
37*4882a593Smuzhiyun  One for each core interrupt priority level. In addition to the combined
38*4882a593Smuzhiyun  interrupt sources, individual megamodule interrupts may be cascaded to
39*4882a593Smuzhiyun  the core interrupt controller. When an individual interrupt is cascaded,
40*4882a593Smuzhiyun  it is no longer handled through a megamodule interrupt combiner and is
41*4882a593Smuzhiyun  considered to have the core interrupt controller as the parent.
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun  Required properties:
44*4882a593Smuzhiyun  --------------------
45*4882a593Smuzhiyun  - compatible: "ti,c64x+megamod-pic"
46*4882a593Smuzhiyun  - interrupt-controller
47*4882a593Smuzhiyun  - #interrupt-cells: <1>
48*4882a593Smuzhiyun  - reg: base address and size of register area
49*4882a593Smuzhiyun  - interrupts: This should have four cells; one for each interrupt combiner.
50*4882a593Smuzhiyun                The cells contain the core priority interrupt to which the
51*4882a593Smuzhiyun                corresponding combiner output is wired.
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun  Optional properties:
54*4882a593Smuzhiyun  --------------------
55*4882a593Smuzhiyun  - ti,c64x+megamod-pic-mux: Array of 12 cells correspnding to the 12 core
56*4882a593Smuzhiyun                             priority interrupts. The first cell corresponds to
57*4882a593Smuzhiyun                             core priority 4 and the last cell corresponds to
58*4882a593Smuzhiyun                             core priority 15. The value of each cell is the
59*4882a593Smuzhiyun                             megamodule interrupt source which is MUXed to
60*4882a593Smuzhiyun                             the core interrupt corresponding to the cell
61*4882a593Smuzhiyun                             position. Allowed values are 4 - 127. Mapping for
62*4882a593Smuzhiyun                             interrupts 0 - 3 (combined interrupt sources) are
63*4882a593Smuzhiyun                             ignored.
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun  Interrupt Specifier Definition
66*4882a593Smuzhiyun  ------------------------------
67*4882a593Smuzhiyun  Single cell specifying the megamodule interrupt source (4-127). Note that
68*4882a593Smuzhiyun  interrupts mapped directly to the core with "ti,c64x+megamod-pic-mux" will
69*4882a593Smuzhiyun  use the core interrupt controller as their parent and the specifier will
70*4882a593Smuzhiyun  be the core priority level, not the megamodule interrupt number.
71*4882a593Smuzhiyun
72*4882a593Smuzhiyun  Examples
73*4882a593Smuzhiyun  --------
74*4882a593Smuzhiyun  megamod_pic: interrupt-controller@1800000 {
75*4882a593Smuzhiyun	compatible = "ti,c64x+megamod-pic";
76*4882a593Smuzhiyun	interrupt-controller;
77*4882a593Smuzhiyun	#interrupt-cells = <1>;
78*4882a593Smuzhiyun	reg = <0x1800000 0x1000>;
79*4882a593Smuzhiyun	interrupt-parent = <&core_pic>;
80*4882a593Smuzhiyun	interrupts = < 12 13 14 15 >;
81*4882a593Smuzhiyun  };
82*4882a593Smuzhiyun
83*4882a593Smuzhiyun  This is a minimal example where all individual interrupts go through a
84*4882a593Smuzhiyun  combiner. Combiner-0 is mapped to core interrupt 12, combiner-1 is mapped
85*4882a593Smuzhiyun  to interrupt 13, etc.
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun
88*4882a593Smuzhiyun  megamod_pic: interrupt-controller@1800000 {
89*4882a593Smuzhiyun	compatible = "ti,c64x+megamod-pic";
90*4882a593Smuzhiyun	interrupt-controller;
91*4882a593Smuzhiyun	#interrupt-cells = <1>;
92*4882a593Smuzhiyun	reg = <0x1800000 0x1000>;
93*4882a593Smuzhiyun	interrupt-parent = <&core_pic>;
94*4882a593Smuzhiyun	interrupts = < 12 13 14 15 >;
95*4882a593Smuzhiyun	ti,c64x+megamod-pic-mux = <  0  0  0  0
96*4882a593Smuzhiyun                                    32  0  0  0
97*4882a593Smuzhiyun                                     0  0  0  0 >;
98*4882a593Smuzhiyun  };
99*4882a593Smuzhiyun
100*4882a593Smuzhiyun  This the same as the first example except that megamodule interrupt 32 is
101*4882a593Smuzhiyun  mapped directly to core priority interrupt 8. The node using this interrupt
102*4882a593Smuzhiyun  must set the core controller as its interrupt parent and use 8 in the
103*4882a593Smuzhiyun  interrupt specifier value.
104