1*4882a593SmuzhiyunSTMicroelectronics STi System Configuration Controlled IRQs 2*4882a593Smuzhiyun----------------------------------------------------------- 3*4882a593Smuzhiyun 4*4882a593SmuzhiyunOn STi based systems; External, CTI (Core Sight), PMU (Performance Management), 5*4882a593Smuzhiyunand PL310 L2 Cache IRQs are controlled using System Configuration registers. 6*4882a593SmuzhiyunThis driver is used to unmask them prior to use. 7*4882a593Smuzhiyun 8*4882a593SmuzhiyunRequired properties: 9*4882a593Smuzhiyun- compatible : Should be set to one of: 10*4882a593Smuzhiyun "st,stih415-irq-syscfg" 11*4882a593Smuzhiyun "st,stih416-irq-syscfg" 12*4882a593Smuzhiyun "st,stih407-irq-syscfg" 13*4882a593Smuzhiyun "st,stid127-irq-syscfg" 14*4882a593Smuzhiyun- st,syscfg : Phandle to Cortex-A9 IRQ system config registers 15*4882a593Smuzhiyun- st,irq-device : Array of IRQs to enable - should be 2 in length 16*4882a593Smuzhiyun- st,fiq-device : Array of FIQs to enable - should be 2 in length 17*4882a593Smuzhiyun 18*4882a593SmuzhiyunOptional properties: 19*4882a593Smuzhiyun- st,invert-ext : External IRQs can be inverted at will. This property inverts 20*4882a593Smuzhiyun these IRQs using bitwise logic. A number of defines have been 21*4882a593Smuzhiyun provided for convenience: 22*4882a593Smuzhiyun ST_IRQ_SYSCFG_EXT_1_INV 23*4882a593Smuzhiyun ST_IRQ_SYSCFG_EXT_2_INV 24*4882a593Smuzhiyun ST_IRQ_SYSCFG_EXT_3_INV 25*4882a593SmuzhiyunExample: 26*4882a593Smuzhiyun 27*4882a593Smuzhiyunirq-syscfg { 28*4882a593Smuzhiyun compatible = "st,stih416-irq-syscfg"; 29*4882a593Smuzhiyun st,syscfg = <&syscfg_cpu>; 30*4882a593Smuzhiyun st,irq-device = <ST_IRQ_SYSCFG_PMU_0>, 31*4882a593Smuzhiyun <ST_IRQ_SYSCFG_PMU_1>; 32*4882a593Smuzhiyun st,fiq-device = <ST_IRQ_SYSCFG_DISABLED>, 33*4882a593Smuzhiyun <ST_IRQ_SYSCFG_DISABLED>; 34*4882a593Smuzhiyun st,invert-ext = <(ST_IRQ_SYSCFG_EXT_1_INV | ST_IRQ_SYSCFG_EXT_3_INV)>; 35*4882a593Smuzhiyun}; 36