1*4882a593Smuzhiyun* SPEAr Shared IRQ layer (shirq)
2*4882a593Smuzhiyun
3*4882a593SmuzhiyunSPEAr3xx architecture includes shared/multiplexed irqs for certain set
4*4882a593Smuzhiyunof devices. The multiplexor provides a single interrupt to parent
5*4882a593Smuzhiyuninterrupt controller (VIC) on behalf of a group of devices.
6*4882a593Smuzhiyun
7*4882a593SmuzhiyunThere can be multiple groups available on SPEAr3xx variants but not
8*4882a593Smuzhiyunexceeding 4. The number of devices in a group can differ, further they
9*4882a593Smuzhiyunmay share same set of status/mask registers spanning across different
10*4882a593Smuzhiyunbit masks. Also in some cases the group may not have enable or other
11*4882a593Smuzhiyunregisters. This makes software little complex.
12*4882a593Smuzhiyun
13*4882a593SmuzhiyunA single node in the device tree is used to describe the shared
14*4882a593Smuzhiyuninterrupt multiplexor (one node for all groups). A group in the
15*4882a593Smuzhiyuninterrupt controller shares config/control registers with other groups.
16*4882a593SmuzhiyunFor example, a 32-bit interrupt enable/disable config register can
17*4882a593Smuzhiyunaccommodate up to 4 interrupt groups.
18*4882a593Smuzhiyun
19*4882a593SmuzhiyunRequired properties:
20*4882a593Smuzhiyun  - compatible: should be, either of
21*4882a593Smuzhiyun     - "st,spear300-shirq"
22*4882a593Smuzhiyun     - "st,spear310-shirq"
23*4882a593Smuzhiyun     - "st,spear320-shirq"
24*4882a593Smuzhiyun  - interrupt-controller: Identifies the node as an interrupt controller.
25*4882a593Smuzhiyun  - #interrupt-cells: should be <1> which basically contains the offset
26*4882a593Smuzhiyun    (starting from 0) of interrupts for all the groups.
27*4882a593Smuzhiyun  - reg: Base address and size of shirq registers.
28*4882a593Smuzhiyun  - interrupts: The list of interrupts generated by the groups which are
29*4882a593Smuzhiyun    then connected to a parent interrupt controller. Each group is
30*4882a593Smuzhiyun    associated with one of the interrupts, hence number of interrupts (to
31*4882a593Smuzhiyun    parent) is equal to number of groups. The format of the interrupt
32*4882a593Smuzhiyun    specifier depends in the interrupt parent controller.
33*4882a593Smuzhiyun
34*4882a593SmuzhiyunExample:
35*4882a593Smuzhiyun
36*4882a593SmuzhiyunThe following is an example from the SPEAr320 SoC dtsi file.
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38*4882a593Smuzhiyunshirq: interrupt-controller@b3000000 {
39*4882a593Smuzhiyun	compatible = "st,spear320-shirq";
40*4882a593Smuzhiyun	reg = <0xb3000000 0x1000>;
41*4882a593Smuzhiyun	interrupts = <28 29 30 1>;
42*4882a593Smuzhiyun	#interrupt-cells = <1>;
43*4882a593Smuzhiyun	interrupt-controller;
44*4882a593Smuzhiyun};
45