1*4882a593Smuzhiyun* ARC-HS Interrupt Distribution Unit 2*4882a593Smuzhiyun 3*4882a593Smuzhiyun This optional 2nd level interrupt controller can be used in SMP configurations 4*4882a593Smuzhiyun for dynamic IRQ routing, load balancing of common/external IRQs towards core 5*4882a593Smuzhiyun intc. 6*4882a593Smuzhiyun 7*4882a593SmuzhiyunProperties: 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun- compatible: "snps,archs-idu-intc" 10*4882a593Smuzhiyun- interrupt-controller: This is an interrupt controller. 11*4882a593Smuzhiyun- #interrupt-cells: Must be <1> or <2>. 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun Value of the first cell specifies the "common" IRQ from peripheral to IDU. 14*4882a593Smuzhiyun Number N of the particular interrupt line of IDU corresponds to the line N+24 15*4882a593Smuzhiyun of the core interrupt controller. 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun The (optional) second cell specifies any of the following flags: 18*4882a593Smuzhiyun - bits[3:0] trigger type and level flags 19*4882a593Smuzhiyun 1 = low-to-high edge triggered 20*4882a593Smuzhiyun 2 = NOT SUPPORTED (high-to-low edge triggered) 21*4882a593Smuzhiyun 4 = active high level-sensitive <<< DEFAULT 22*4882a593Smuzhiyun 8 = NOT SUPPORTED (active low level-sensitive) 23*4882a593Smuzhiyun When no second cell is specified, the interrupt is assumed to be level 24*4882a593Smuzhiyun sensitive. 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun The interrupt controller is accessed via the special ARC AUX register 27*4882a593Smuzhiyun interface, hence "reg" property is not specified. 28*4882a593Smuzhiyun 29*4882a593SmuzhiyunExample: 30*4882a593Smuzhiyun core_intc: core-interrupt-controller { 31*4882a593Smuzhiyun compatible = "snps,archs-intc"; 32*4882a593Smuzhiyun interrupt-controller; 33*4882a593Smuzhiyun #interrupt-cells = <1>; 34*4882a593Smuzhiyun }; 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun idu_intc: idu-interrupt-controller { 37*4882a593Smuzhiyun compatible = "snps,archs-idu-intc"; 38*4882a593Smuzhiyun interrupt-controller; 39*4882a593Smuzhiyun interrupt-parent = <&core_intc>; 40*4882a593Smuzhiyun #interrupt-cells = <1>; 41*4882a593Smuzhiyun }; 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun some_device: serial@c0fc1000 { 44*4882a593Smuzhiyun interrupt-parent = <&idu_intc>; 45*4882a593Smuzhiyun interrupts = <0>; /* upstream idu IRQ #24 */ 46*4882a593Smuzhiyun }; 47