1*4882a593Smuzhiyun* ARC-HS incore Interrupt Controller (Provided by cores implementing ARCv2 ISA)
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3*4882a593SmuzhiyunProperties:
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5*4882a593Smuzhiyun- compatible: "snps,archs-intc"
6*4882a593Smuzhiyun- interrupt-controller: This is an interrupt controller.
7*4882a593Smuzhiyun- #interrupt-cells: Must be <1>.
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9*4882a593Smuzhiyun  Single Cell "interrupts" property of a device specifies the IRQ number
10*4882a593Smuzhiyun  between 16 to 256
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12*4882a593Smuzhiyun  intc accessed via the special ARC AUX register interface, hence "reg" property
13*4882a593Smuzhiyun  is not specified.
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15*4882a593SmuzhiyunExample:
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17*4882a593Smuzhiyun	intc: interrupt-controller {
18*4882a593Smuzhiyun		compatible = "snps,archs-intc";
19*4882a593Smuzhiyun		interrupt-controller;
20*4882a593Smuzhiyun		#interrupt-cells = <1>;
21*4882a593Smuzhiyun		interrupts = <16 17 18 19 20 21 22 23 24 25>;
22*4882a593Smuzhiyun	};
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