1*4882a593SmuzhiyunSigma Designs SMP86xx/SMP87xx secondary interrupt controller
2*4882a593Smuzhiyun
3*4882a593SmuzhiyunRequired properties:
4*4882a593Smuzhiyun- compatible: should be "sigma,smp8642-intc"
5*4882a593Smuzhiyun- reg: physical address of MMIO region
6*4882a593Smuzhiyun- ranges: address space mapping of child nodes
7*4882a593Smuzhiyun- interrupt-controller: boolean
8*4882a593Smuzhiyun- #address-cells: should be <1>
9*4882a593Smuzhiyun- #size-cells: should be <1>
10*4882a593Smuzhiyun
11*4882a593SmuzhiyunOne child node per control block with properties:
12*4882a593Smuzhiyun- reg: address of registers for this control block
13*4882a593Smuzhiyun- interrupt-controller: boolean
14*4882a593Smuzhiyun- #interrupt-cells: should be <2>, interrupt index and flags per interrupts.txt
15*4882a593Smuzhiyun- interrupts: interrupt spec of primary interrupt controller
16*4882a593Smuzhiyun
17*4882a593SmuzhiyunExample:
18*4882a593Smuzhiyun
19*4882a593Smuzhiyuninterrupt-controller@6e000 {
20*4882a593Smuzhiyun	compatible = "sigma,smp8642-intc";
21*4882a593Smuzhiyun	reg = <0x6e000 0x400>;
22*4882a593Smuzhiyun	ranges = <0x0 0x6e000 0x400>;
23*4882a593Smuzhiyun	interrupt-parent = <&gic>;
24*4882a593Smuzhiyun	interrupt-controller;
25*4882a593Smuzhiyun	#address-cells = <1>;
26*4882a593Smuzhiyun	#size-cells = <1>;
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun	irq0: interrupt-controller@0 {
29*4882a593Smuzhiyun		reg = <0x000 0x100>;
30*4882a593Smuzhiyun		interrupt-controller;
31*4882a593Smuzhiyun		#interrupt-cells = <2>;
32*4882a593Smuzhiyun		interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
33*4882a593Smuzhiyun	};
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun	irq1: interrupt-controller@100 {
36*4882a593Smuzhiyun		reg = <0x100 0x100>;
37*4882a593Smuzhiyun		interrupt-controller;
38*4882a593Smuzhiyun		#interrupt-cells = <2>;
39*4882a593Smuzhiyun		interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
40*4882a593Smuzhiyun	};
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun	irq2: interrupt-controller@300 {
43*4882a593Smuzhiyun		reg = <0x300 0x100>;
44*4882a593Smuzhiyun		interrupt-controller;
45*4882a593Smuzhiyun		#interrupt-cells = <2>;
46*4882a593Smuzhiyun		interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
47*4882a593Smuzhiyun	};
48*4882a593Smuzhiyun};
49