1*4882a593SmuzhiyunRISC-V Hart-Level Interrupt Controller (HLIC) 2*4882a593Smuzhiyun--------------------------------------------- 3*4882a593Smuzhiyun 4*4882a593SmuzhiyunRISC-V cores include Control Status Registers (CSRs) which are local to each 5*4882a593SmuzhiyunCPU core (HART in RISC-V terminology) and can be read or written by software. 6*4882a593SmuzhiyunSome of these CSRs are used to control local interrupts connected to the core. 7*4882a593SmuzhiyunEvery interrupt is ultimately routed through a hart's HLIC before it 8*4882a593Smuzhiyuninterrupts that hart. 9*4882a593Smuzhiyun 10*4882a593SmuzhiyunThe RISC-V supervisor ISA manual specifies three interrupt sources that are 11*4882a593Smuzhiyunattached to every HLIC: software interrupts, the timer interrupt, and external 12*4882a593Smuzhiyuninterrupts. Software interrupts are used to send IPIs between cores. The 13*4882a593Smuzhiyuntimer interrupt comes from an architecturally mandated real-time timer that is 14*4882a593Smuzhiyuncontrolled via Supervisor Binary Interface (SBI) calls and CSR reads. External 15*4882a593Smuzhiyuninterrupts connect all other device interrupts to the HLIC, which are routed 16*4882a593Smuzhiyunvia the platform-level interrupt controller (PLIC). 17*4882a593Smuzhiyun 18*4882a593SmuzhiyunAll RISC-V systems that conform to the supervisor ISA specification are 19*4882a593Smuzhiyunrequired to have a HLIC with these three interrupt sources present. Since the 20*4882a593Smuzhiyuninterrupt map is defined by the ISA it's not listed in the HLIC's device tree 21*4882a593Smuzhiyunentry, though external interrupt controllers (like the PLIC, for example) will 22*4882a593Smuzhiyunneed to define how their interrupts map to the relevant HLICs. This means 23*4882a593Smuzhiyuna PLIC interrupt property will typically list the HLICs for all present HARTs 24*4882a593Smuzhiyunin the system. 25*4882a593Smuzhiyun 26*4882a593SmuzhiyunRequired properties: 27*4882a593Smuzhiyun- compatible : "riscv,cpu-intc" 28*4882a593Smuzhiyun- #interrupt-cells : should be <1>. The interrupt sources are defined by the 29*4882a593Smuzhiyun RISC-V supervisor ISA manual, with only the following three interrupts being 30*4882a593Smuzhiyun defined for supervisor mode: 31*4882a593Smuzhiyun - Source 1 is the supervisor software interrupt, which can be sent by an SBI 32*4882a593Smuzhiyun call and is reserved for use by software. 33*4882a593Smuzhiyun - Source 5 is the supervisor timer interrupt, which can be configured by 34*4882a593Smuzhiyun SBI calls and implements a one-shot timer. 35*4882a593Smuzhiyun - Source 9 is the supervisor external interrupt, which chains to all other 36*4882a593Smuzhiyun device interrupts. 37*4882a593Smuzhiyun- interrupt-controller : Identifies the node as an interrupt controller 38*4882a593Smuzhiyun 39*4882a593SmuzhiyunFurthermore, this interrupt-controller MUST be embedded inside the cpu 40*4882a593Smuzhiyundefinition of the hart whose CSRs control these local interrupts. 41*4882a593Smuzhiyun 42*4882a593SmuzhiyunAn example device tree entry for a HLIC is show below. 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun cpu1: cpu@1 { 45*4882a593Smuzhiyun compatible = "riscv"; 46*4882a593Smuzhiyun ... 47*4882a593Smuzhiyun cpu1-intc: interrupt-controller { 48*4882a593Smuzhiyun #interrupt-cells = <1>; 49*4882a593Smuzhiyun compatible = "sifive,fu540-c000-cpu-intc", "riscv,cpu-intc"; 50*4882a593Smuzhiyun interrupt-controller; 51*4882a593Smuzhiyun }; 52*4882a593Smuzhiyun }; 53